DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Amendments filed 3/30/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-15, 17, 18, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP-H04-356974-A (a copy of which was already by Applicant on 9/12/2022).
Regarding claim 1, ‘974 discloses a semiconductor device (Figs. 6-7 which is a device including a “semiconductor relay”, Title of ‘974) comprising:
a package substrate (entirety of Figs. 6-7) including a package member (40) and a first conductive portion (see annotated figures below);
a semiconductor package (unlabeled in Fig. 6, corresponding to “photovoltaic element 3 in Fig. 2; Abstract of ‘974) provided on a first surface of the package substrate (top surface of 41 in Fig. 7) inside the package member (“inside the package member” is interpreted as within the lateral boundaries of the package member) and coupled to the first conductive portion (as Applicant set forth in the specification the concept of components being “directly coupled” but claimed only “coupled”, “coupled” is interpreted to allow for intervening components);
a first semiconductor chip (5a in Fig. 6) provided on the first surface of the package substrate inside the package member and including a first terminal (terminal contacting the wire connected to the first conductive portion);
a second semiconductor chip (5b) provided on the first surface of the package substrate inside the package member, including a second terminal (terminal contacting the wire connected to the first conductive portion), and arranged side by side with the first semiconductor chip in a first direction parallel to the first surface (see annotated figures below); and
a connection component (the plurality of wires connected to the first conductive portion in Fig. 6) that couples the first and second terminals to the first conductive portion inside the package member, wherein:
the first conductive portion includes:
a first portion (see annotated figures below) provided between the first semiconductor chip and the second semiconductor chip, arrange side by side with the semiconductor package in a second direction parallel to the first surface and intersecting the first direction, and coupled to the connection component (see annotated figures), and
a second portion continuous with the first portion, provided between the first portion and the semiconductor package in the second direction, and coupled to the semiconductor package, and
the second portion includes:
one end connected to the first portion, and
another end continuous with the one end of the second portion in the first direction and adjacent to the first portion via a slit in the second direction (see annotated figures).
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Regarding claim 5, ‘974 further discloses wherein the first conductive portion is located between the first semiconductor chip and the second semiconductor chip (see Fig. 6).
Regarding claim 6, ‘974 further discloses wherein the package substrate further includes:
a second conductive portion (portion connected to wire 43) including a first lead portion (tip connected to wire 43) and a second lead portion (tip connected to wire from 5b) continuous with the first lead portion, the first lead portion passes through a region (region extending across the entire package substrate which is directly above 32 and directly below 3 in Fig. 1) which is below the semiconductor package in a third direction perpendicular to the first surface and between one end of the semiconductor package in the second direction and another end of the semiconductor package in the second direction (as the first lead portion is below the semiconductor package, the region through which it extends is also below the semiconductor package), and extends from a first end side of the package substrate toward a second end side of the package substrate in the first direction beyond the semiconductor package, and the second lead portion passes through a region which is below the semiconductor package in the third direction (as the second lead portion is below the semiconductor package, the region through which it extends is also below the semiconductor package) and extends from the first lead portion toward the first conductive portion in the second direction (see Fig. 6).
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Regarding claim 7, ‘974 further discloses wherein the first semiconductor chip includes a third terminal, the second semiconductor chip includes a fourth terminal, the third terminal is coupled to the first lead portion via a first wire, and the fourth terminal is coupled to the first lead portion via a second wire (see above).
Regarding claim 8, ‘974 further discloses the second conductive portion has a T-shaped planar shape as viewed in a direction perpendicular to the first surface (see Fig. 6).
Regarding claim 9, ‘974 further discloses wherein the package substrate further includes: a first die pad (die pad under first semiconductor chip) on which the first semiconductor chip is arranged; a second die pad (die pad under second semiconductor chip) on which the second semiconductor chip is arranged; a third conductive portion coupled to a fifth terminal of the semiconductor package; and a fourth conductive portion coupled to a sixth terminal of the semiconductor package.
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Regarding claim 10, ‘974 further discloses wherein the package substrate further includes: a first connection terminal provided on a second surface side of the package substrate (second surface side being on the top surface of the conductive traces) which is opposite to the first surface in a third direction perpendicular to the first surface, overlapping the first die pad in the third direction, and coupled to the first die pad; a second connection terminal provided on the second surface side, overlapping the second die pad in the third direction, and coupled to the second die pad; a third connection terminal provided on the second surface side, overlapping the third conductive portion in the third direction, and coupled to the third conductive portion; and a fourth connection terminal provided on the second surface side, overlapping the fourth conductive portion in the third direction, and coupled to the fourth conductive portion (see above).
Regarding claim 11, ‘974 further discloses wherein the first to fourth connection terminals are exposed from the second surface (see Fig. 6).
Regarding claim 12, ‘974 further discloses wherein the semiconductor package is arranged in a region between the first semiconductor chip and the second semiconductor chip, and the first and second semiconductor chips are arranged on the package substrate symmetrically, with a line passing through a center of the semiconductor package as an axis of symmetry (see Fig. 6).
Regarding claim 13, ‘974 further discloses wherein the semiconductor package include an optical coupling device (“photocoupler”, Title).
Regarding claim 14, ‘974 further discloses wherein each of the first and second semiconductor chips includes a transistor (“mos transistors”, ¶ 0008).
Regarding claim 15, ‘974 further discloses wherein the semiconductor package includes: a package layer (conductor connected to the left side of wire 43 in Fig. 6) covered with the package member (using an orientation opposite of that shown in Fig. 7 as the device is operable when rotated); and a circuit portion (wire 43) covered with the package layer.
Regarding claim 17, ‘974 further discloses wherein the connection component includes a wire (see Fig. 6).
Regarding claim 18, ‘974 further discloses wherein the first and second semiconductor chips are sealed by the package member (the bottom surface of the chips are sealed by the package member).
Regarding claim 21, ‘974 discloses a semiconductor device (Figs. 6-7 which is a device including a “semiconductor relay”, Title of ‘974) comprising:
a package substrate (entirety of Figs. 6-7) including a package member (40), a first conductive portion (see annotated figures below), and a second conductive portion (portion connected to wire 43);
a semiconductor package (unlabeled in Fig. 6, corresponding to “photovoltaic element 3 in Fig. 2; Abstract of ‘974) provided on a first surface of the package substrate (top surface of 41 in Fig. 7) inside the package member (“inside the package member” is interpreted as within the lateral boundaries of the package member) and coupled to the first conductive portion (as Applicant set forth in the specification the concept of components being “directly coupled” but claimed only “coupled”, “coupled” is interpreted to allow for intervening components);
a first semiconductor chip (5a in Fig. 6) provided on the first surface of the package substrate inside the package member and including a first terminal (terminal contacting the wire connected to the first conductive portion);
a first die pad (die pad under first semiconductor chip) which is provided in the package substrate, on which the first semiconductor chip is arranged on the first surface of the package substrate, which is coupled to the first semiconductor chip, and which has a first connection terminal provided on a second surface side of a second surface of the package substrate, the second surface being opposite to the first surface in a first direction perpendicular to the first surface, the first connection terminal being exposed from the second surface (see Figs. 6-7);
a second semiconductor chip (5b) provided on the first surface of the package substrate inside the package member and including a second terminal (terminal contacting the wire connected to the first conductive portion);
a connection component (the plurality of wires connected to the first conductive portion in Fig. 6) that couples the first and second terminals to the first conductive portion inside the package member, wherein
the second conductive portion includes a first lead portion (tip connected to wire 43) and a second lead portion (tip connected to wire from 5b) continuous with the first lead portion,
the first lead portion passes through a region (region extending across the entire package substrate which is directly above 32 and directly below 3 in Fig. 1) which is below the semiconductor package in a first direction perpendicular to the first surface and between one end of the semiconductor package in the second direction, and extends from a first end side of the package substrate toward a second end side of the package substrate in a third direction parallel to the first surface and intersecting the second direction beyond the semiconductor package (see Fig. 1), and
the second lead portion passes through a region (region extending across the entire package substrate which is directly above 32 and directly below 3 in Fig. 1) which is below the semiconductor package in the first direction and extends from the first lead portion toward the first conductive portion in the second direction (see Fig. 1).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘974 as applied to claim 1 above, and further in view of Rubin et al. (US 2021/0159211 A1).
Regarding claim 16, ’974 differs from the claimed invention by the substitution of a connection component comprising copper with a connection component that is not explicitly disclosed as comprising copper. However, connection components comprising copper and the corresponding function was known in the art (¶ 0044 of Rubin). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known element of copper connection components as taught by Rubin for the connection component material of ‘974 and the results of the substitution would have been predictable as an electrical conductor. (see MPEP § 2143(I)(B)).
Regarding claim 19, ’974 differs from the claimed invention by the substitution of a package substrate comprising ceramic with a package substrate that is not explicitly disclosed as comprising ceramic. However, package substrates comprising ceramic and the corresponding function was known in the art (¶ 0064 of Rubin). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known element of ceramic package substrates as taught by Rubin for the package substrate material of ‘974 and the results of the substitution would have been predictable as a packing substrate to support overlying components. (see MPEP § 2143(I)(B)).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP-H04-356974-A (a copy of which was already by Applicant on 9/12/2022).
Regarding claim 20, ‘974 discloses a semiconductor device (Figs. 6-7 which is a device including a “semiconductor relay”, Title of ‘974) comprising:
a package substrate (entirety of Figs. 6-7) including a package member (40) and a first conductive portion (see annotated figures below);
a semiconductor package (unlabeled in Fig. 6, corresponding to “photovoltaic element 3 in Fig. 2; Abstract of ‘974) provided on a first surface of the package substrate (top surface of 41 in Fig. 7) inside the package member (“inside the package member” is interpreted as within the lateral boundaries of the package member) and coupled to the first conductive portion (as Applicant set forth in the specification the concept of components being “directly coupled” but claimed only “coupled”, “coupled” is interpreted to allow for intervening components);
a first semiconductor chip (5a in Fig. 6) provided on the first surface of the package substrate inside the package member and including a first terminal (terminal contacting the wire connected to the first conductive portion);
a second semiconductor chip (5b) provided on the first surface of the package substrate inside the package member, including a second terminal (terminal contacting the wire connected to the first conductive portion), and arranged side by side with the first semiconductor chip in a first direction parallel to the first surface (see annotated figures below);
a second pad (pad under the second semiconductor chip) which is provided in the package substrate, on which the second semiconductor chip is arranged on a first surface side of the first surface of the package substrate, which is coupled to the second semiconductor chip, and which has a second connection terminal provided on the second surface side of the package substrate, the second connection terminal being exposed from the second surface (see Figs. 6-7); and
a connection component (the plurality of wires connected to the first conductive portion in Fig. 6) that couples the first and second terminals to the first conductive portion inside the package member.
‘974 does not disclose wherein the first semiconductor chip is arranged side by side with the second semiconductor chip in a second direction parallel to the first surface, the semiconductor package is arranged in a region between the first semiconductor chip and the second semiconductor chip, and the first and second semiconductor chips are arranged on the package substrate symmetrically, with a line passing through a center of the semiconductor package as an axis of symmetry. However, arranging the first and second semiconductor chips such that the first semiconductor chip is arranged side by side with the second semiconductor chip in a second direction parallel to the first surface, the semiconductor package is arranged in a region between the first semiconductor chip and the second semiconductor chip, and the first and second semiconductor chips are arranged on the package substrate symmetrically, with a line passing through a center of the semiconductor package as an axis of symmetry amounts to rearranging the first and second semiconductor chips and, as such, would have been obvious to one having ordinary skill in the art (see MPEP 2144.04(VI)(C)).
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Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive.
Applicant argues that JP ‘974 does not disclose or suggest the newly added limitations. This argument is not persuasive as ‘974 does disclose the newly added limitations, as discussed in the rejection of claim 1 above.
Applicant further argues that “Two MOS type transistors mounted on a substrate are not equivalent to first and second semiconductor chips”. This argument is not persuasive as MOS type transistors include silicon which is a semiconductor and the transistors are chips.
Applicant further argus that JP ‘974 does not disclose the features of claim 21. This argument is not persuasive as ‘974 discloses the features of claim 21 as discussed in the rejection of claim 21 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.C/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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