Prosecution Insights
Last updated: August 17, 2026
Application No. 17/942,814

SEMICONDUCTOR MEMORY DEVICE

Non-Final OA §103
Filed
Sep 12, 2022
Priority
Jan 26, 2022 — RE 10-2022-0011531
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
42%
Grant Probability
Moderate
1-2
OA Rounds
0m
Est. Remaining
49%
With Interview

Examiner Intelligence

Grants 42% of resolved cases
42%
Career Allowance Rate
145 granted / 343 resolved
-25.7% vs TC avg
Moderate +7% lift
Without
With
+6.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
43 currently pending
Career history
418
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
59.1%
+19.1% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
23.2%
-16.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 343 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 15-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/24/2025. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 8-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai (US 2021/0398577 A1) in view of Zhuang et al. (“Nonpolar Resistive Switching of Multilayer-hBN-Based Memories”; Adv. Electron. Mater., 2019). Regarding claim 1, Lai discloses a semiconductor memory device (Fig. 3) comprising a memory cell (Fig. 3), the memory cell comprising: a memory unit (106) for storing data; and a selection element unit (104) electrically connected to the memory unit and including a first electrode layer (306), a second electrode layer (302), and a selection element layer (304) that includes an insulating material layer doped with a dopant (¶ 0029) and is interposed between the first electrode layer and the second electrode layer (see Fig. 3). Lai does not disclose wherein the insulating material layer has a two-dimensional crystalline structure. However, two-dimensional crystalline structures and the corresponding function of selection elements was known in the art (Abstract of Zhuang). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known composition of two-dimensional crystalline structure as taught by Zhuang for the insulator material of Lai and the results of the substitution would have been predictable to serve as a selection element layer in a semiconductor memory device. (see MPEP § 2143(I)(B)). In the resulting configuration, the insulating material will still be doped as Lai discloses that the dopant is used to tune the threshold voltage (¶ 0029). Regarding claim 2, Zhuang discloses that the insulating material includes hexagonal boron nitride (Abstract of Zhuang). Regarding claim 3, as Applicant discloses that doped hexagonal boron nitride will include a shallow trap created by the dopant and, thereby, provide a passageway for conductive carriers, the insulating material layer of the device of the combination will include a shallow trap created by the dopant and, thereby, provide a passageway for conductive carriers. Regarding claim 4, Lai discloses that the energy level may be tuned (¶ 0029). Adjusting the energy level of the shallow trap to bet greater than a work function of at least one of the first electrode layer and the second electrode layer therefore amounts to determining the workable ranges of the energy level by routine experimentation and have a reasonable expectation of success. It is, therefore, obvious to one having ordinary skill in the art (MPEP 2144.05(II)(A)). Regarding claim 5, the insulating material layer in the selection element layer of the device of the combination includes dangling bonds, wherein a density of the dangling bonds of the insulating material layer is smaller than a density of dangling bonds of an amorphous insulating material (as Applicant discloses that hexagonal boron nitride has this property and the insulating material layer in the selection element layer of the device of the combination is hexagonal boron nitride). Regarding claim 8, Lai further discloses a plurality of lower conductive interconnection structures (BL in Fig. 7) extending in a first direction; and a plurality of upper conductive interconnect structures (SL) extending in a second direction intersecting the first direction, wherein the memory cell is interposed between the lower conductive interconnect structures and the upper conductive interconnect structures at each intersection of the lower conductive interconnect structures and the upper conductive interconnect structures (See Fig. 7). Regarding claim 9, Lai discloses a semiconductor memory device (Fig. 6D) comprising a memory cell wherein the cell is structured to store data and includes: a first electrode (306) disposed on a substrate (602); a selector (304) including an insulating material layer doped with a dopant structure (¶ 0029) and formed on the first electrode to exhibit different electrically conductive states depending on whether a voltage applied thereto is above or below a threshold voltage to select or de-select the memory cell for a memory operation; and a second electrode (302) disposed on the selector so that the first and second electrodes are connected to apply the voltage to the selector. Lai does not disclose wherein the insulating material layer has a two-dimensional crystalline structure. However, two-dimensional crystalline structures and the corresponding function of selection elements was known in the art (Abstract of Zhuang). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known composition of two-dimensional crystalline structure as taught by Zhuang for the insulator material of Lai and the results of the substitution would have been predictable to serve as a selection element layer in a semiconductor memory device. (see MPEP § 2143(I)(B)). In the resulting configuration, the insulating material will still be doped as Lai discloses that the dopant is used to tune the threshold voltage (¶ 0029). Regarding claim 10, Zhuang discloses that the insulating material includes hexagonal boron nitride (Abstract of Zhuang). Regarding claim 11, as Applicant discloses that doped hexagonal boron nitride will include a shallow trap created by the dopant and, thereby, provide a passageway for conductive carriers, the insulating material layer of the device of the combination will include a shallow trap created by the dopant and, thereby, provide a passageway for conductive carriers. Regarding claim 12, Lai discloses that the energy level may be tuned (¶ 0029). Adjusting the energy level of the shallow trap to bet greater than a work function of at least one of the first electrode layer and the second electrode layer therefore amounts to determining the workable ranges of the energy level by routine experimentation and have a reasonable expectation of success. It is, therefore, obvious to one having ordinary skill in the art (MPEP 2144.05(II)(A)). Regarding claim 14, each memory cell includes a variable resistance material (106 in Fig. 6D of Lai) that stores data by changing a resistance of the variable resistance material (Abstract of Lai). Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai (US 2021/0398577 A1) in view of Zhuang et al. (“Nonpolar Resistive Switching of Multilayer-hBN-Based Memories”; Adv. Electron. Mater., 2019) as applied to claim 1 above and further in view of Oliveira et al. (“Electronic and optical properties of Ge doped graphene and BN monolayers”, Applied Physics A (2019)). Regarding claim 6, Lai does not disclose the particulars of the energy level modifying dopant to determine if it has a valence different from a valance of at least one of the elements that constitute the insulating material layer. Oliveira discloses that germanium may be used to dope boron nitride layers (Abstract of Oliveira). There was a benefit to using germanium as the dopant in that it can reduce the gap energy (Conclusion of Oliveira). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use germanium as the dopant to achieve this benefit. As germanium has a valance different from boron, the claim limitation is satisfied. Regarding claim 7, Lai does not disclose the particulars of the energy level modifying dopant to determine if it is one of the claimed elements. Oliveira discloses that germanium may be used to dope boron nitride layers (Abstract of Oliveira). There was a benefit to using germanium as the dopant in that it can reduce the gap energy (Conclusion of Oliveira). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use germanium as the dopant to achieve this benefit. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai (US 2021/0398577 A1) in view of Zhuang et al. (“Nonpolar Resistive Switching of Multilayer-hBN-Based Memories”; Adv. Electron. Mater., 2019) as applied to claim 9 above and further in view of Oliveira et al. (“Electronic and optical properties of Ge doped graphene and BN monolayers”, Applied Physics A (2019)). Regarding claim 13, Lai does not disclose the particulars of the energy level modifying dopant to determine if it is one of the claimed elements. Oliveira discloses that germanium may be used to dope boron nitride layers (Abstract of Oliveira). There was a benefit to using germanium as the dopant in that it can reduce the gap energy (Conclusion of Oliveira). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use germanium as the dopant to achieve this benefit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Sep 12, 2022
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701913
LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS
5y 12m to grant Granted Aug 04, 2026
Patent 12701701
METHODS FOR FABRICATION OF 3-DIMENSIONAL NOR MEMORY ARRAYS
4y 4m to grant Granted Aug 04, 2026
Patent 12701917
PYROELECTRIC DEVICE FOR A SEMICONDUCTOR DEVICE
4y 1m to grant Granted Aug 04, 2026
Patent 12684991
DISPLAY PANEL AND METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE
3y 12m to grant Granted Jul 14, 2026
Patent 12677583
DISPLAY PANEL AND METHOD FOR REPAIRING SAME
4y 4m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
42%
Grant Probability
49%
With Interview (+6.7%)
3y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 343 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month