DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 19, 21 and 22 rejected
Present action: claims 1 through 19, 21 and 22 rejected
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 17, and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The below listing is not considered exhaustive, every claim should be reviewed for clarity and accordance with USC 112.
Claim 2 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the interface shim layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 22 recites the limitation "the interface shim layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the second physical interface" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the second physical interface" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the second physical interface" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation "the second physical interface" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the first physical interface" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the first physical interface" in line 1. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination the examiner, in order to maintain consistency amongst claims and with the specification, will assume that “first physical interface” refers to “a tightly-coupled physical interface layer” that interfaces with the memory stack, and “second physical interface” refers to “an application specific integrated circuitry interface layer” that interfaces with the ASIC.
Claim 12 recites “the second physical interface is configured to facilitate communication with the application specific integrated circuit and the second physical interface via a plurality of through silicon vias”. The claim is unclear because it states that the second physical interface is communicating with itself through TSVs, this is ambiguously self referential. The examiner believes that the claim intended for the physical interface layer in the shim to communicate with a physical interface layer in the ASIC through TSVs as is shown in figure 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) in view of Klein (US 2020/0343234)
Regarding claim 1.
Baek teaches:
A memory device, comprising: a plurality of stacked memory die (fig 1a:500; [para 0051]);
an application specific integrated circuit (fig 1a:200; [para 0046]);
and an interface shim layer (fig 1a:400; [para 0050]);
wherein the interface shim layer (fig 1a:400; [para 0050]) is directly coupled to at least one memory die (fig 1a:500; [para 0051]) of the plurality of stacked memory die (fig 1a:500; [para 0051]) and is separate from the application specific integrated circuit (fig 1a:200; [para 0046]);
wherein the interface shim layer (fig 1a:400; [para 0050]) is configured to directly couple to the application specific integrated circuit (fig 1a:200; [para 0046]);
and wherein the interface shim layer (fig 1a:400; [para 0050]) is configured to facilitate communication between the plurality of stacked memory die (fig 1a:500; [para 0051]) and the application specific integrated circuit (fig 1a:200; [para 0046]) via a routing layer (fig 1a:410; [para 0057]), , and an application specific integrated circuity interface layer (fig 1a:440; [para 0057]), each residing in the interface shim layer (fig 1a:400; [para 0050]).
Baek does not teach a tightly coupled physical interface layer residing in the interface shim.
Biswas teaches:
a tightly-coupled physical interface layer (fig 3:60e; [para 0033]), and an application integrated circuity interface layer (fig 3:60a; [para 0033]), each residing in the interface shim layer (fig 3:18; [para 0033]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a tightly coupled physical interface layer in order to interface between the shim layer and the memory stack.
Baek does not state that interface shim layer comprises active components.
Klein teaches:
An active (fig 5:124; [para 0040])interface shim layer (fig 5:502; [para 0040])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the components of the shim layer are active components so that the interface layer has the ability to decode requests, read requests and responsively transmit signals (paragraph 40).
Regarding claim 2.
Baek in view of Biswas in view of Klein teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 14:400; [para 0098]) further comprises a through-silicon via (fig 14) configured to serve as an interconnect between the interface shim layer (fig 14:400; [para 0098]) and the plurality of stacked memory die (fig 14:500; [para 0051]).
Regarding claim 3.
Baek in view of Biswas in view of Klein teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) comprises a plurality of wires (fig 1a:411,412; [para 0057]) configured to facilitate coupling ([para 0058]) of the plurality of stacked memory die (fig 1a:500; [para 0051]) to the application specific integrated circuit (fig 1a:200; [para 0046]) via the interface shim layer (fig 1a:400; [para 0050]).
Regarding claim 4.
Baek in view of Biswas in view of Klein teaches the memory device of claim 1, further
Baek teaches:
the memory device further comprises a plurality of bumps (fig 1a:507; [para 0052]) configured to interconnect at least one memory die (fig 1a:510; [para 0052]) of the plurality of stacked memory die (fig 1a:500; [para 0051]) with at least one other memory die (fig 1a:520; [para 0052]) of the plurality of stacked memory die (fig 1a:500; [para 0051]).
Regarding claim 5.
Baek in view of Biswas in view of Klein teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is further configured to communicate with the application specific integrated circuit (fig 1a:200; [para 0046]) via a physical interface layer (fig 1a:210; [para 0063]) of the application specific integrated circuit (fig 1a:200; [para 0046]).
Regarding claim 7.
Baek in view of Biswas in view of Klein teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is further configured to include a physical interface (fig 1a:440; [para 0057,0058]) configured to include input output circuits (fig 1a:430; [para 0057,0058]) configured to communicate with the plurality of stacked memory die (fig 1a:500; [para 0051]).
Biswas teaches:
a first physical interface (fig 3:60e; [para 0033]) configured to communicate with the plurality of stacked memory die (fig 3:16a-16d; [para 0033]).
Regarding claim 8
Baek in view of Biswas in view of Klein teaches the memory device of claim 7, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is further configured to include a physical interface (fig 1a:440; [para 0057,0058]) configured to communicate ([para 0061]) with the application specific integrated circuit (fig 1a:200; [para 0046])
Baek in view of Klein does not state that the shim comprises a second physical interface.
Biswas teaches:
the interface shim layer (fig 3:18; [para 0032]) is further configured to include a second physical interface (fig 3:60a; [para 0033]) configured to communicate with the application integrated circuit (fig 3:12; [para 0033]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) in view of Klein (US 2020/0343234) as applied to claim 1 and further in view of Kang (US 2014/0151892)
Regarding claim 6.
Baek in view of Biswas in view of Klein teaches the memory device of claim 1
Baek teaches:
the memory device further comprises a package substrate (fig 1a:100; [para 0045]) upon which the plurality of stacked memory die (fig 1a:500; [para 0051]), the interface shim layer (fig 1a:400; [para 0050]), and the application specific integrated circuit (fig 1a:200; [para 0046]) are disposed.
Baek in view of Biswas in view of Klein does not teach a silicon package substrate.
Kang teaches:
the memory device further comprises a package substrate (fig 1:108; [para 0013]) comprising silicon ([para 0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the package substrate to comprise silicon due to silicon having a compatible coefficient of thermal expansion, minimal contamination risks, and processing compatibility.
Claim(s) 9, 10, 11, 12, 16, 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) in view of Klein (US 2020/0343234)
Regarding claim 9
A memory device, comprising: a plurality of stacked memory die (fig 1a:500; [para 0051]);
an application specific integrated circuit (fig 1a:200; [para 0046]);
and an interface shim layer (fig 1a:400; [para 0050]);
wherein the interface shim layer (fig 1a:400; [para 0050]) is directly coupled to at least one memory die (fig 1a:510; [para 0052]) of the plurality of stacked memory die (fig 1a:500; [para 0051]) and comprising a plurality of input output circuits (fig 1a,1c:430,433,431; [para 0060])configured to communicate ([para 0060]) with the plurality of stacked memory die (fig 1a:500; [para 0051]);
and wherein the interface shim layer (fig 1a:400; [para 0050]) comprises an application specific integrated circuit interface layer (fig 1a:440; [para 0057])residing in the active interface shim layer (fig 1a:400; [para 0050]) and comprising a plurality of input output circuits (fig 1a,1c:430,431,433; [para 0060]) configured to communicate ([para 0061]) to and from an application specific integrated circuit (fig 1a:200; [para 0046]), wherein the interface shim layer (fig 1a:400; [para 0050]) is configured to directly couple to the application specific integrated circuit (fig 1a:200; [para 0046]) and is separate from the application specific integrated circuit (fig 1a:200; [para 0046]).
Baek does not teach a separate physical interface circuit in the interface shim and coupled to the memory stack.
Biswas teaches:
wherein the interface shim layer (fig 3:18; [para 0033]) is directly coupled to at least one memory die of the plurality of stacked memory die (fig 3:16a-16d; [para 0033]) and comprises a tightly-coupled physical interface layer (fig 3:60a; [para 0032]) residing in the active interface shim layer (fig 3:18; [para 0033])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a physical interface for the ASIC in order to optimize the data path design (paragraph 28).
Baek does not state that interface shim layer comprises active components.
Klein teaches:
An active (fig 5:124; [para 0040])interface shim layer (fig 5:502; [para 0040])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the components of the shim layer are active components so that the interface layer has the ability to decode requests, read requests and responsively transmit signals (paragraph 40).
Regarding claim 10
Baek in view of Klein in view of Biswas teaches the memory device of claim 9, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) further comprises a plurality of routing layers (fig 1a:411,412; [para 0057,0058]) .
Biswas teaches:
the interface layer further (fig 3:18; [para 0033]) is configured to facilitate communication between the first physical interface (fig 3:60e; [para 0033]) and the second physical interface (fig 3:60a; [para 0033]).
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Regarding claim 11.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) further comprises a plurality of through silicon vias (fig 11:460; [para 0088]) configured to facilitate communication with the plurality of stacked memory die (fig 11:500; [para 0088]).
Biswas teaches:
the interface shim layer (fig 3,13:18; [para 0049]) configured to facilitate communication with the plurality of stacked memory die (fig 3,12:16a-16d[para 0028])
Regarding claim 12.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9, further
Baek teaches:
the (application specific integrated circuit interface layer residing in the active interface shim layer) (fig 1a:440; [para 0057]) is configured to facilitate communication with the application specific integrated circuit (fig 1a:200; [para 0046]) and the (a physical interface layer residing in the application specific integrated circuit) (fig 1a:210; [para 0063]) via a plurality of through silicon vias (fig 1a:230; [para 0063]).
Regarding claim 16.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9, further
Baek teaches:
the physical interface layer (fig 1a:440; [para 0057]) comprises a plurality of input output circuits (fig 1a:430,431,433; [para 0057,0060]) that are configured to communicate with the plurality of stacked memory die (fig 1a:500; [para 0057]).
Biswas teaches:
the (tightly-coupled) physical interface (fig 3:60f; [para 0033]) configured to communicate with the plurality of stacked memory die (fig 3:16a-16d; [para 0033]).
Regarding claim 17.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9, further
Baek teaches:
the physical interface (fig 1a:440; [para 0061]) comprises a plurality of input output circuits (fig 1a:430,431,433; [para 0060,0061]) that are configured to communicate ([para 0061]) with the application specific integrated circuit (fig 1a:200; [para 0046]).
Biswas teaches:
a second physical interface (fig 3:60a; [para 0033])configured to communicate with the integrated circuit (fig 3:12; [para 0033]).
Regarding claim 18.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9, further
Baek teaches:
the plurality of stacked memory die (fig 1a:500; [para 0051]) comprise tightly-controlled random access memory die.
Regarding claim 19.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9, further
Baek teaches:
the memory device further comprises a plurality of bumps (fig 1a:507; [para 0052])configured to interconnect the plurality of stacked memory die (fig 1a:500; [para 0051]).
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) in view of Klein (US 2020/0343234) as applied to claim 9 and further in view of Kegel (US 2014/0089609)
Regarding claim 13.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9,
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) further configured to manage communication and control the plurality of stacked memory die (fig 1a:500; [para 0051]).
Baek in view of Biswas in view of Klein does not teach the shim comprises a memory controller.
Kegel teaches:
the interface shim layer (fig 1:110; [para 0050]) further comprises a memory controller (fig 1:130-1; [para 0050]) configured to manage communication and control the plurality memory die (fig 1:140-1,140-2; [para 0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the interposer with a memory controller interfaces between a processor and one or more memory devices, and manages the flow of data between the processor and the memory device (paragraph 12)
Regarding claim 14.
Baek in view of Biswas in view of Klein in view of Kegel teaches the memory device of claim 13, further,
Kegel teaches:
wherein the memory controller (fig 1:130-1; [para 0050]) is configured to provide a scheduler function, timing control, memory refresh management, data first-in first-outs, error correction, floor sweeping, reliability, availability, and serviceability functionality, or a combination thereof ([para 0050]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) in view of Klein (US 2020/0343234) as applied to claim 9 and further in view of Hsu (US 2021/0375837)
Regarding claim 15.
Baek in view of Biswas in view of Klein teaches the memory device of claim 9,
Baek in view of Biswas in view of Klein does not teach the shim comprises test circuitry.
Hsu teaches:
the interface shim layer (fig 2:10; [para 0051]) further comprise a built-in self-test circuit configured to test functionality of the plurality of stacked memory die, repair the plurality of stacked memory die, or a combination thereof ([para 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the shim to comprise circuitry in order that the shim is able to coordinate the distribution of signals between the external processors and the memory devices
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) in view of Klein (US 2020/0343234)
Regarding claim 21.
Baek teaches:
A memory device, comprising: a plurality of stacked memory die (fig 1a:500; [para 0051]); an application specific integrated circuit (fig 1a:200; [para 0046]);
and an interface shim layer (fig 1a:400; [para 0050]), comprising;
comprising input output circuits (fig 1a:430,433,431; [para 0057]) configured to communicate to and from the plurality of stacked memory die (fig 1a:500; [para 0051];
and an application specific integrated circuit interface layer comprising input output circuits (fig 1a:430,433,431; [para 0057]) configured to communicate ([para 0061]) to and from the application specific integrated circuit (fig 1a:200; [para 0046]), wherein the interface shim layer (fig 1a:400; [para 0050]) is separate from the application specific integrated circuit (fig 1a:200; [para 0046]).
Baek does not teach an additional tightly coupled physical interface layer configured to communicate to the stacked memory die.
Biswas teaches:
an interface shim layer (fig 3:18; [para 0033]), comprising; a tightly-coupled physical interface layer (fig 3:60f; [para 0033]) comprising configured to communicate to and from the plurality of stacked memory die (fig 3:16a-16d; [para 0033]);
and an application integrated circuit interface layer (fig 3:60a; [para 0033])configured to communicate to and from the application integrated circuit (fig 3:12; [para 0033]), wherein the interface shim layer (fig 3:18; [para 0033]) is separate from the application integrated circuit (fig 3:12; [para 0033]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a tightly coupled physical interface layer in order to interface between the shim layer and the memory stack.
Baek does not state that interface shim layer comprises active components.
Klein teaches:
An active (fig 5:124; [para 0040])interface shim layer (fig 5:502; [para 0040])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the components of the shim layer are active components so that the interface layer has the ability to decode requests, read requests and responsively transmit signals (paragraph 40).
Regarding claim 22.
Baek in view of Biswas in view of Klein teaches the memory device of claim 21, further:
wherein the interface shim layer (fig 1a:400; [para 0050]) is directly coupled to at least one of the plurality of stacked memory die (fig 1a:500; [para 0051]) and the application specific integrated circuit (fig 1a:200; [para 0046]),
Response to Arguments
The previously applied rejection over 112 2nd paragraph are moot due to amendment.
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not state that the shim comprises active circuitry.
Although Baek in view of Biswas does not state that the shim comprises active circuitry, the prior art does teach that the shim comprises physical interface, input, and output circuitry which is used to control the communication between the processor and the memory stack. Klein explicitly teaches that such circuitry is active circuitry. The combination is obvious because active circuitry can be actively controlled to actively direct communication between the adjacent layers.
The applicant argues that the cache Dram architecture is not the active shim layer of the claimed invention. However, the applicant provides no distinguishing features that support this argument.
The applicant argues that the prior art shows the physical interface layer residing in the ASIC whereas the applicant claims the physical interface layer is in the shim layer.
This argument is not commensurate with the applicant’s disclosure. The applicant clearly illustrates (fig 6) that the ASIC comprises physical interface circuitry (628) that is coupled to the physical interface circuitry (614) of the shim layer which is connected to additional physical interface circuitry (612) which is connected to the memory stack. This arrangement is substantially the same as the arrangement disclosed in Biswas.
A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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