DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Claim Status
Previous action: claims 1 through 19, 21, and 22 rejected
Present action: claims 1 through 19, 21 and 22 rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 11 recites “the application specific integrated circuit” in line 11. The antecedence of the limitation is unclear because Claim 1 recites “an application specific integrated circuit” in line 8 and 9, and “an application specific integrated circuit” is recited in line 3.
Further, claim 3 recites “the application specific integrated circuit” in line 3. It is unclear if this refers to line 3 or line 8 of claim 1.
Further, claim 5 recites “the application specific integrated circuit” in line 3. It is unclear if this refers to line 3 or line 8 of claim 1.
Further, claim 6 recites “the application specific integrated circuit” in line 3. It is unclear if this refers to line 3 or line 8 of claim 1.
For the purpose of examination claim 1 line 8 will be interpreted as “the
Claims 2 through 8 depend from and incorporate claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 5, and 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Baek (US 2022/0028848).
Regarding claim 1.
Baek teaches:
A memory device, comprising:
a plurality of stacked memory die (fig 1a:500; [para 0051]);
an application specific integrated circuit (fig 1a:200; [para 0046]);
and an interface shim layer (fig 1a:400; [para 0050]);
wherein the interface shim layer (fig 1a:400; [para 0050]) is directly coupled to at least one memory die (fig 1a:510; [para 0051])of the plurality of stacked memory die (fig 1a:500; [para 0051]) and is separate from the application specific integrated circuit (fig 1a:200; [para 0046]);
wherein the interface shim layer (fig 1a:400; [para 0050]) is configured (fig 1a:410; [para 0057]) to directly couple to an application specific integrated circuit (fig 1a:200; [para 0046]);
and wherein the interface shim layer (fig 1a:400; [para 0050]) is configured to facilitate communication between the plurality of stacked memory die (fig 1a:500; [para 0051]) and the application specific integrated circuit (fig 1a:200; [para 0046]) via a routing layer (fig 1a:430,440; [para 0057]) residing in the interface shim layer (fig 1a:400; [para 0050]).
Regarding claim 2.
Baek teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 14:400; [para 0098]) further comprises a through-silicon via (fig 14) configured to serve as an interconnect between the interface shim layer (fig 14:400; [para 0098]) and the plurality of stacked memory die (fig 14:500; [para 0051]).
Regarding claim 3.
Baek teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) comprises a plurality of wires (fig 1a:411,412; [para 0057]) configured to facilitate coupling ([para 0058]) of the plurality of stacked memory die (fig 1a:500; [para 0051]) to the application specific integrated circuit (fig 1a:200; [para 0046]) via the interface shim layer (fig 1a:400; [para 0050]).
Regarding claim 4.
Baek teaches the memory device of claim 1, further
Baek teaches:
the memory device further comprises a plurality of bumps (fig 1a:507; [para 0052]) configured to interconnect at least one memory die (fig 1a:510; [para 0052]) of the plurality of stacked memory die (fig 1a:500; [para 0051]) with at least one other memory die (fig 1a:520; [para 0052]) of the plurality of stacked memory die (fig 1a:500; [para 0051]).
Regarding claim 5.
Baek teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is further configured to communicate with the application specific integrated circuit (fig 1a:200; [para 0046]) via a physical interface layer (fig 1a:210; [para 0063]) of the application specific integrated circuit (fig 1a:200; [para 0046]).
Regarding claim 7.
Baek teaches the memory device of claim 1, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is further configured to include a first physical interface (fig 1a:440; [para 0057,0058]) configured to include input output circuits (fig 1a:430; [para 0057,0058]) configured to communicate with the plurality of stacked memory die (fig 1a:500; [para 0051]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) as applied to claim 1 and further in view of Kang (US 2014/0151892)
Regarding claim 6.
Baek teaches the memory device of claim 1
Baek teaches:
the memory device further comprises a package substrate (fig 1a:100; [para 0045]) upon which the plurality of stacked memory die (fig 1a:500; [para 0051]), the interface shim layer (fig 1a:400; [para 0050]), and the application specific integrated circuit (fig 1a:200; [para 0046]) are disposed.
Baek does not teach a silicon package substrate.
Kang teaches:
the memory device further comprises a package substrate (fig 1:108; [para 0013]) comprising silicon ([para 0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the package substrate to comprise silicon due to silicon having a compatible coefficient of thermal expansion, minimal contamination risks, and processing compatibility.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) as applied to claim 7 and further in view of Biswas (US 2019/0198083)
Regarding claim 8.
Baek teaches the memory device of claim 7, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is configured to communicate with the application specific integrated circuit (fig 1a:200; [para 0046])
Baek does not states that the shim comprises a second physical interface.
Biswas teaches:
the interface shim layer (fig 3:18; [para 0032]) is further configured to include a second physical interface (fig 3:60a; [para 0033]) configured to communicate with the circuit (fig 3:12; [para 0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a physical interface for the ASIC in order to optimize the data path design (paragraph 28).
Claim(s) 9, 10, 11, 12, 16, 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083)
Regarding claim 9.
Baek teaches:
A memory device, comprising: a plurality of stacked memory die (fig 1a:500; [para 0051]);
and an interface shim layer (fig 1a:400; [para 0050]);
wherein the interface shim layer (fig 1a:400; [para 0050]) is directly coupled to at least one memory die (fig 1a:510; [para 0052])of the plurality of stacked memory die (fig 1a:500; [para 0051]) and comprises a first physical interface (fig 1a:440; [para 0057]) residing in the interface shim layer (fig 1a:400; [para 0050]) and configured to facilitate communication to and from ([para 0057]) the plurality of stacked memory die (fig 1a:500; [para 0051]);
and wherein the interface shim layer (fig 1a:400; [para 0050]) and configured to facilitate communication to and from ([para 0063]) an application specific integrated circuit (fig 1a:200; [para 0046]),
wherein the interface shim layer (fig 1a:400; [para 0050]) is configured to directly couple to the application specific integrated circuit (fig 1a:200; [para 0046]) and is separate from the application specific integrated circuit (fig 1a:200; [para 0046]).
Baek does not teach a second physical interface in the shim.
Biswas teaches:
wherein the interface layer (fig 3:18; [para 0033]) comprises a second physical interface (fig 3:60a; [para 0032]) residing in the interface layer (fig 3:18; [para 0033]) and configured to facilitate communication to and from a circuit (fig 3:12; [para 0033]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a physical interface for the ASIC in order to optimize the data path design (paragraph 28).
Regarding claim 10
Baek in view of Biswas teaches the memory device of claim 9, further
Baek teaches the interface shim layer (fig 1a:400; [para 0050]) further comprises a plurality of routing layers (fig 1a:411,412; [para 0057,0058]) .
Biswas teaches:
the interface layer further (fig 3:18; [para 0033]) is configured to facilitate communication between the first physical interface (fig 3:60e; [para 0033]) and the second physical interface (fig 3:60a; [para 0033]).
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Regarding claim 11.
Baek in view of Biswas teaches the memory device of claim 9, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) further comprises a plurality of through silicon vias (fig 11:460; [para 0088]) configured to facilitate communication with the plurality of stacked memory die (fig 11:500; [para 0088]).
Biswas teaches:
the interface shim layer (fig 3,13:18; [para 0049]) configured to facilitate communication with the plurality of stacked memory die (fig 3,12:16a-16d[para 0028])
Regarding claim 12.
Baek teaches:
the physical interface (fig 1a:440; [para 0057]) is configured to facilitate communication with the application specific integrated circuit (fig 1a:200; [para 0046]) and the second physical interface (fig 1a:440; [para 0057]) via a plurality of through silicon vias (fig 1a:230; [para 0063]).
Regarding claim 16.
Baek in view of Biswas teaches the memory device of claim 9, further
Baek teaches:
the first physical interface (fig 1a:440; [para 0057]) comprises a plurality of input output circuits (fig 1a:430,431,433; [para 0057,0060]) that are configured to communicate with the plurality of stacked memory die (fig 1a:500; [para 0057]).
Regarding claim 17.
Baek in view of Biswas teaches the memory device of claim 9, further
Baek teaches:
the physical interface (fig 1a:440; [para 0061]) comprises a plurality of input output circuits (fig 1a:430,431,433; [para 0060,0061]) that are configured to communicate with the application specific integrated circuit (fig 1a:200; [para 0046]).
Biswas teaches:
a second physical interface (fig 3:60a; [para 0033])
Regarding claim 18.
Baek in view of Biswas teaches the memory device of claim 9, further
Baek teaches:
the plurality of stacked memory die (fig 1a:500; [para 0051]) comprise tightly-controlled random access memory die.
Regarding claim 19.
Baek in view of Biswas teaches the memory device of claim 9, further
Baek teaches:
the memory device further comprises a plurality of bumps (fig 1a:507; [para 0052])configured to interconnect the plurality of stacked memory die (fig 1a:500; [para 0051]).
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) as applied to claim 9 and further in view of Kegel (US 2014/0089609)
Regarding claim 13.
Baek in view of Biswas teaches the memory device of claim 9,
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) further configured to manage communication and control the plurality of stacked memory die (fig 1a:500; [para 0051]).
Baek in view of Biwas does not teach the shim comprises a memory controller.
Kegel teaches:
the interface shim layer (fig 1:110; [para 0050]) further comprises a memory controller (fig 1:130-1; [para 0050]) configured to manage communication and control the plurality memory die (fig 1:140-1,140-2; [para 0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the interposer with a memory controller interfaces between a processor and one or more memory devices, and manages the flow of data between the processor and the memory device (paragraph 12)
Regarding claim 14.
Baek in view of Biswas in view of Kegel teaches the memory device of claim 13, further,
Kegel teaches:
wherein the memory controller (fig 1:130-1; [para 0050]) is configured to provide a scheduler function, timing control, memory refresh management, data first-in first-outs, error correction, floor sweeping, reliability, availability, and serviceability functionality, or a combination thereof ([para 0050]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083) as applied to claim 9 and further in view of Hsu (US 2021/0375837)
Regarding claim 15.
Baek in view of Biswas teaches the memory device of claim 9,
Baek in view of Biswas does not teach the shim comprises test circuitry.
Hsu teaches:
the interface shim layer (fig 2:10; [para 0051]) further comprise a built-in self-test circuit configured to test functionality of the plurality of stacked memory die, repair the plurality of stacked memory die, or a combination thereof ([para 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the shim to comprise circuitry in order that the shim is able to coordinate the distribution of signals between the external processors and the memory devices
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2022/0028848) in view of Biswas (US 2019/0198083)
Regarding claim 21.
Baek teaches:
A memory device, comprising:
a plurality of stacked memory die (fig 1a:500; [para 0051]);
an application specific integrated circuit (fig 1a:200; [para 0046]);
and an interface shim layer (fig 1a:400; [para 0050]), comprising; a first physical interface layer configured to facilitate communication ([para 0058]) to and from the plurality of stacked memory die (fig 1a:500; [para 0051]);
and configured to facilitate communication to and from the application specific integrated circuit (fig 1A:200; [para 0057]), wherein the interface shim layer (fig 1a:400; [para 0050]) is separate from the application specific integrated circuit (fig 1A:200; [para 0057]).
Baek does not teach a second physical interface in the shim.
Biswas teaches:
wherein the interface shim layer (fig 3:18; [para 0032]) comprises a second physical interface (fig 3:60a; [para 0033]) configured to facilitate communication to and from a circuit (fig 3:12; [para 0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a physical interface for the ASIC in order to optimize the data path design (paragraph 28).
Regarding claim 22.
Baek in view of Biswas teaches the memory device of claim 21, further
Baek teaches:
the interface shim layer (fig 1a:400; [para 0050]) is directly coupled to at least one (fig 1a:510; [para 0051]) of the plurality of stacked memory die (fig 1a:500; [para 0057]) and the application specific integrated circuit (fig 1A:200; [para 0057]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on the reference combination as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
The applicant argues that Baek and Biswas do not teach a shim layer (page 2).
However, it is unclear from the applicant’s disclosure what the applicant considers to be an interface shim or how it is distinct from the interface die (400) disclosed by Baek or the interface die (18) disclosed by Biswas. For the purpose of examination the examiner has interpreted an interface shim to be a die providing an interface between a processor and a memory stack. There is no reason provided in the applicant’s disclosure or in the prior art why this would exclude a die comprising memory cache, or any other die comprising the required physical interface layer
The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).
To act as their own lexicographer, the applicant must clearly set forth a special definition of a claim term in the specification that differs from the plain and ordinary meaning it would otherwise possess. CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366, 62 USPQ2d 1658, 1662 (Fed. Cir. 2002).
The applicant argues that examiner conflates routing circuits within a cache dram chip with routing circuits in a separate shim.
This is incorrect. The examiner clearly interpreted the interface die (18) taught by Biswas as an interface shim due to the fact that the die acts as an interface between a processor and a die stack. As noted above, the applicant provides no teaching or interpretation that would exclude such an interpretation.
The applicant argues that Biswas does not teach the shim layer is separate from the processor layer because the pins that connect PHY 24 to phy 26 are directly connected (page 2 and 3).
This statement supports the examiner position because, as the applicant notes, the shim comprises separate physical interface circuits 24. Further, as can be seen in applicant’s figure 6, the shim 610 comprises physical interface circuits and the ASIC 620 comprises physical interface circuits. Therefore, there is no reason to believe that the presence of physical interface within the shim is precluded by additional physical interface circuits within the processor
The applicant argues that Baek merely discloses an interposer comprising routing circuitry (page 3).
As far as can be determined from the applicant’s disclosure, this is what the applicant means by an active shim. The applicant provides no teaching or definition that conflicts with such an interpretation. From the applicant’s disclosure a shim is a silicon die that comprises routing and may or may not comprise active circuitry. The applicant’s provides no reasoning as to why a shim excludes a memory cache
The applicant argues that Baek does not teach PHY is separate from the processor because it is on the processor.
This is an erroneous statement. Baek was clearly referring to the relative physical placement of the PHY circuitry within the die 400 over die 200 (see fig 1a), this proper interpretation is supported by Baek paragraph 57 lines 1 through 3 “the interposer 400 may include a routing circuit 410, an input/output (I/O) circuit 430, and a first physical layer (PHY) 440.”
The applicant argues that Baek and Biswas do not teach a shim layer that is separate from the processor and includes a routing layer within the shim layer facilitating communication.
This is incorrect. Baek figure 1a clearly shows a shim layer (400) that is separate from the processor (200) and comprises its own routing (410,411,412,430,440) facilitating communication. Also Biswas figure 13 teaches a shim layer (phy 24) that is separate from the processor (12) and comprises routing circuitry (phy 24) facilitating communication.
The applicant argues that Baek teaches physical interface circuitry that is split between devices and not located within one device (page 4).
The applicant is incorrect. Baek clearly and explicitly teaches and shows that physical interface circuitry (24) is located within one device. The fact that interface circuitry interfaces with other interface circuitry does not negate this. For reference, this is like how the presence of interface circuitry 628 in ASIC 620 does not negate the presence of interface circuitry 614 in die 610 in applicant’s figure 6.
The applicant argues that Biswas fails to teach a second physical interface circuitry in the shim because figure 1 does not show a second physical interface circuitry.
However, Biswas figure 3 shows within a shim layer first physical interface circuitry (60e) facilitating communication with the dram and second physical interface circuitry (60a) facilitating communication with a processor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 10, 2026
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