DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 through 5, 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biswas (US 2019/0198083) in view of Baek (US 2022/0028848)
Regarding claim 1.
Biswas teaches a memory device, comprising: a plurality of stacked memory die (16a-16d); and an interface shim layer (18,24); wherein the interface shim layer (18,24) is directly coupled to at least one memory die (16d) of the plurality of stacked memory die (16a-16d); wherein the interface shim layer (18,24) is configured to directly couple to an integrated circuit (12) (fig 13) (paragraph 49); and wherein the interface shim layer (18,24) is configured to facilitate communication between the plurality of stacked memory die (16a-16d) and the integrated circuit (12) via a routing layer (phy circuits) of the interface shim layer (18,24) (paragraph 49) (fig 13).
Biswas does not teach an application specific integrated circuit (ASIC)
Baek teaches a memory device, comprising: a plurality of stacked memory die (500); and an interface layer (400); wherein the interface layer (400) is directly coupled to at least one memory die (510) of the plurality of stacked memory die (500) (paragraph 49); wherein the interface layer (400) is configured to directly couple to an application specific integrated circuit (ASIC) (200) (paragraph 46); and wherein the interface layer is configured to facilitate communication between the plurality of stacked memory die (500) and the application specific integrated circuit (ASIC) (200) via a routing layer (411,412) of the interface layer (paragraph 57) (fig 1a).
It would have been obvious to one of ordinary skill in the art for the integrated circuit to comprise an application specific integrated circuit in order to for the device to be optimized for a specific application.
Regarding claim 2.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 1.
Biswas further teaches the interface shim layer (18,24) further comprises a through-silicon via configured to serve as an interconnect between the interface shim layer and the plurality of stacked memory die (16a-16d) (paragraph 45,46).
Regarding claim 3.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 1.
Biswas further teaches the interface shim layer (18,24) comprises a plurality of wires configured to facilitate coupling of the plurality of stacked memory die (164-16d) to the integrated circuit (12) via the interface shim layer (18,24) (paragraph 49) (fig 13).
Regarding claim 4.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 1.
Biswas further teaches the memory device further comprises a plurality of bumps (paragraph 47) configured to interconnect at least one memory die of the plurality of stacked memory die (16a-16d) with at least one other memory die of the plurality of stacked memory die (fig 13).
Regarding claim 5.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 1.
Biswas further teaches the interface shim layer (18,24) is further configured to communicate with the integrated circuit (12) via a physical interface layer (60d) of the integrated circuit (fig 2,13) (paragraph 32,49).
Baek teaches the interface shim layer is further configured to communicate with the application specific integrated circuit (200) via a physical interface layer (210) of the application specific integrated circuit (200) (paragraph 63).
Regarding claim 7.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 1.
Biswas further teaches the interface shim layer (18,24) is further configured to include a first physical interface (60c) configured to include input output circuits configured to communicate with the plurality of stacked memory die (16a-16d) (fig 2,13) (paragraph 32,49).
Regarding claim 8.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 7.
Biswas teaches the interface shim layer (18,24) is further configured to include a second physical interface (60b) configured to communicate with the integrated circuit (12) (fig 2,13) (paragraph 32,49).
Baek teaches the interface shim layer is further configured to communicate with the application specific integrated circuit (200) via a physical interface layer (210) of the application specific integrated circuit (200) (paragraph 63).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biswas (US 2019/0198083) in view of Baek (US 2022/0028848) as applied to claim 1 and furth in view of Kang (US 2014/0151892)
Regarding claim 6.
Biswas in view of Baek teaches elements of the claimed invention above in the rejection of claim 1.
Baek teaches a package substrate (100) upon which the plurality of stacked memory die (500), the interface layer (400), and the application specific integrated circuit (200) are disposed (fig 1a) (paragraph 45).
Biswas in view of Baek does not teach a silicon package substrate.
Kang teaches the memory device further comprises a package substrate (108) comprising silicon (fig 1) (paragraph 13).
It would have been obvious to one of ordinary skill in the art to provide a silicon package substrate in order for the substrate to match the thermal properties of the overlying die.
Claim(s) 9, 10, 11, 12, 16, 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biswas (US 2019/0198083) in view of Baek (US 2022/0028848)
Regarding claim 9.
Biswas teaches a memory device, comprising: a plurality of stacked memory die (16a-16d); and an interface shim layer (18,24) (fig 13) (paragraph 49); wherein the interface shim layer (18,24) is directly coupled to at least one memory die (16d) of the plurality of stacked memory die (16a-16d) and comprises a first physical interface (60c) configured to facilitate communication to and from the plurality of stacked memory die (16a-16d) (fig 2) (paragraph 32); and wherein the interface shim layer (18,24) comprises a second physical interface (60b) configured to facilitate communication to and from an integrated circuit (12), wherein the interface shim layer (18,24) is configured to directly couple to the integrated circuit (12) (fig 2,13).
Biswas does not teach an application specific integrated circuit (ASIC)
Baek teaches a memory device, comprising: a plurality of stacked memory die (500); and an interface layer (400); wherein the interface layer (400) is directly coupled to at least one memory die (510) of the plurality of stacked memory die (500) (paragraph 49); wherein the interface layer (400) is configured to directly couple to an application specific integrated circuit (ASIC) (200) (paragraph 46); and wherein the interface layer is configured to facilitate communication between the plurality of stacked memory die (500) and the application specific integrated circuit (200) via a routing layer (411,412) of the interface layer (paragraph 57) (fig 1a).
It would have been obvious to one of ordinary skill in the art for the integrated circuit to comprise an application specific integrated circuit in order to for the device to be optimized for a specific application.
Regarding claim 10.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the interface shim layer (18,24) further comprises routing configured to facilitate communication between the first physical interface (60c) and the second physical interface (60b) (paragraph 28) (fig 2).
Baek teaches the interface layer (400) further comprises a plurality of routing layers (411,412) configured to facilitate communication (fig 1a) (paragraph 58).
Regarding claim 11.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the interface shim layer (18,24) further comprises a plurality of through silicon vias (paragraph 45-47) configured to facilitate communication with the plurality of stacked memory die (16a-16d) (fig 13).
Regarding claim 12.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the second physical interface (60b) is configured to facilitate communication with the integrated circuit (12) and the second physical interface (60b) via a plurality of through silicon vias (fig 2,13) (paragraph 45-49).
Regarding claim 16.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the first physical interface (60c,24) comprises a plurality of input output circuits that are configured to communicate with the plurality of stacked memory die (16a-16d) (paragraph 45).
Regarding claim 17.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the second physical interface (60b,24) comprises a plurality of input output circuits that are configured to communicate with the integrated circuit (12) (fig 2,13) (paragraph 45).
Regarding claim 18.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the plurality of stacked memory die (16a-16d) comprise tightly-controlled random access memory die (fig 13) (paragraph 49).
Regarding claim 19
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Biswas teaches the memory device further comprises a plurality of bumps configured to interconnect the plurality of stacked memory die (16a-16d) (paragraph 47) (fig 13).
Claim(s) 13, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biswas (US 2019/0198083) in view of Baek (US 2022/0028848) as applied to claim 9 and further in view of Goto (US 2021/0313004).
Regarding claim 13.
Biswas in view of Baek teaches elements of the claimed invention above in the rejection od claim 9.
Biswas in view of Baek does not teach the interface shim comprises a memory controller.
Goto teaches the interface shim layer (LD1) further comprises a memory controller (MCNT) configured to manage communication and control the plurality of stacked memory die (MD1-MD4) (fig 2,3) (paragraph 60).
It would have been obvious for the interface shim to comprise a memory controller in order to control access to the unit (Goto paragraph 28).
Regarding claim 14.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 13.
Goto teaches the memory controller is configured to provide a scheduler function, timing control, memory refresh management, data first-in first-outs, error correction, floor sweeping, reliability, availability, and serviceability functionality, or a combination thereof (paragraph 44).
Regarding claim 15.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 9.
Goto teaches the interface shim layer further comprise a built-in self-test circuit configured to test functionality (BIST) of the plurality of stacked memory die, repair (RCR) the plurality of stacked memory die, or a combination thereof (fig 2) (paragraph 60).
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biswas (US 2019/0198083) in view of Baek (US 2022/0028848)
Regarding claim 21.
Biswas teaches a memory device, comprising: a plurality of stacked memory die (16a-16d); an integrated circuit (12); and an interface shim layer (18,24) (fig 13) (paragraph 49), comprising; a first physical interface layer (60c) configured to facilitate communication to and from the plurality of stacked memory die (16a-16d) (fig 2); and a second physical interface layer (60b) configured to facilitate communication to and from the integrated circuit (12) (fig 2) (paragraph 32).
Biswas does not teach an application specific integrated circuit (ASIC)
Baek teaches a memory device, comprising: a plurality of stacked memory die (500); an application specific integrated circuit (200); and an interface layer (400) (fig 1a) (paragraph 49).
It would have been obvious to one of ordinary skill in the art for the integrated circuit to comprise an application specific integrated circuit (ASIC) in order to for the device to be optimized for a specific application.
Regarding claim 22.
Biswas in view of Baek teaches elements of the structure in the rejection of claim 21.
Biswas further teaches the interface shim layer (18,24) is directly coupled to at least one of the plurality of stacked memory die (16d) and the integrated circuit (12).
Baek teaches a memory device, comprising: a plurality of stacked memory die (500); an application specific integrated circuit (200); and an interface layer (400) (fig 1a) (paragraph 49).
Response to Arguments
Applicant's arguments filed 8/29/2025 have been fully considered but they are not persuasive.
The applicant argues that Biswas does not teach an interface shim.
The applicant will note that Biswas teaches a shim chip, although Biswas does not name the chip a shim.
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The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). MPEP 2131.
Biswas explicitly states that the chip facilitates and controls the interface between the stacked die (16A -16D) and the underlying chip (12) (paragraph 49):
“Pins on the bottom side of the SOC 12 (not shown) may be used to couple the SOC into the rest of a system. As mentioned above, other embodiments may have independent PHY circuits 24 for the cache DRAM 18 and for the main DRAMs 16A-16D.“ and “the cache DRAM 18 routes the TSV interconnects to the desired position at the edge of the cache DRAM 18, the TSVs may be more freely placed in the main DRAMs 16A-16D”. (paragraph 46)
(Note PHY circuits are physical interface circuits, paragraph 39). And clearly illustrates, in figure 2, that the PHY circuits control the interface between the DRAM chips 16A-16D and the SOC 12.
The applicant argues that the chip is DRAM cache not an interface shim.
The applicant provides no reasoning as to why the functions would be mutually exclusive. Rather, the applicant explicitly notes that the shim may comprise active circuitry such as control and test circuitry. Biswas explicitly teaches these components are part of the prior art structure, “to further increase density, some control logic to the DRAMs 16A-16D, such as test circuitry, redundancy control, error correction code (ECC) mechanisms, reference voltage logic, temperature control reference logic, etc. may be located on the cache DRAM 18” (paragraph 41).
The applicant argues that Biswas does not teach the shim comprises a physical interface and second physical interface
The applicant is incorrect. Biswas teaches a physical interface (60c) coupled to at least one memory die and a second physical interface (60b).
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In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 September 18, 2025