Attorney Docket Number: U1483.10002US01
Filing Date: 09/12/2022
Claimed Priority Dates: 09/21/2020 (PCT/CN/2020/116503)
05/22/2020 (CN 202010440056.4)
Inventors: Zhu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 06/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “215” has been used to designate both a grating coupler and a semiconductor layer in figure 2C.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “216” has been used to designate both an optical waveguide and a semiconductor layer in figures 2C-2G and 2I.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “217” has been used to designate both a first optional feature (i.e., a first doped area) and a semiconductor layer in figures 2C-2G and 2I.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “218” has been used to designate both a second optional feature (i.e., a second doped area) and a semiconductor layer in figures 2C-2G and 2I.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Iida (US 2020/0161284) in view of Liu (US 2016/0341656).
Regarding claims 10 and 20, Iida (see, e.g., fig. 3) shows most aspects of the instant invention, including a semiconductor integrated circuit MJ comprising a semiconductor device CHP1/CHP2, the semiconductor device comprising:
a first insulating layer BX;
a semiconductor layer WG1/OR/GC (see, e.g., par.0045/ll.1-4) stacked with the first insulator layer;
a substrate SB2 arranged opposite to the semiconductor layer; and
one or more functional layers stacked with each other and located between the semiconductor layer and the substrate
wherein:
the semiconductor layer WG1/OR/GC comprises a grating coupler GC; and
no semiconductor material is provided on an entire surface of the first insulating layer BX that faces away from the semiconductor layer WG1/OR/GC, such that the first insulating layer, instead of the semiconductor material, provides an optical transmission channel (arrow shown between GC and RF2) to couple optical signals in or out (e.g., in or out of layer IF1), wherein the optical transmission channel is between the grating coupler GC and an outside of the semiconductor device RF2 that is located on a side, facing away from the semiconductor layer, of the first insulating layer (see, e.g., pars.0051/ll.1-4 and 0053/ll.14-16)
Although Iida teaches most aspects of the instant invention, Iida fails to specify that Iida’s substrate is a carrier substrate. Liu, in the same field of endeavor, teaches using a carrier substrate as the substrate for a semiconductor device. Liu further teaches that such a carrier substrate can provide a rigid structural support to a remainder of an integrated device (see, e.g., Liu: par.0022/ll.8-11).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use a carrier substrate as the substrate of Iida, as taught by Liu, so as to bolster the structural support of Liu’s integrated circuit and device.
Regarding claim 11, Iida (see, e.g., fig. 3) shows wherein that:
the one or more functional layers comprise a second insulating layer IL2 located on the side of the semiconductor layer WG1/OR/GC that faces away from the first insulating layer BX
the first insulating layer and the second insulating layer have a refractive index less than a refractive index of the semiconductor layer (see, e.g., pars. 0045/ll.1-4, 0056/ll.8-11, and 0066/ll.8-10); and
the semiconductor layer further comprises an optical waveguide WG1 optically coupled to the grating coupler GC
Regarding claim 12, Iida (see, e.g., fig. 3) shows that the one or more functional layers further comprise a patterned conducting layer 1Q, 2Q located on a side of the second insulating layer IL2 that faces away from the semiconductor layer WG1/OR/GC.
Regarding claim 16, Iida (see, e.g., fig. 3) shows that the patterned conducting layer 1Q, 2Q comprises a second pattern part 3Q, wherein an orthogonal projection of the second pattern part on the first insulating layer BX at least partially overlaps with an orthogonal projection of the optical waveguide WG1 on the first insulating layer.
Regarding claim 17, Iida (see, e.g., par.0045/ll.6-8) shows that the first insulating BX has a thickness of 2 µm to 6 µm.
Nevertheless, differences in thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed thickness, i.e., 2 µm to 6 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Iida.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Iida/Liu in view of Meister (US 2019/0146151).
Regarding claim 18, Iida shows most aspects of the instant invention (see paragraphs 9-11 above). Iida (see, e.g., fig. 3) further shows a metal wiring layer M5b located on the side of an insulating layer IL1 that faces away from the semiconductor layer WG1/OR/GC, where an orthogonal projection of the metal wiring layer on the carrier substrate SB2 does not overlap with an orthogonal projection of the grating coupler GC on the carrier substrate. However, Iida fails to specify that the wiring layer is located on the side of the first insulator layer that faces away from the semiconductor layer. Meister, in the same field of endeavor and in a similar device to Iida, shows a wiring layer 44 located on the side of a first insulator layer 11 that faces away from a semiconductor layer 10a comprising a grating coupler 21 (see, e.g., Meister: fig. 4).
Meister is evidence showing that one of ordinary skill in the art would appreciate that having a wiring layer located on the side of a first insulator layer that faces away from a semiconductor layer would be equivalent to a device having a wiring layer located on the side of a different insulator layer that faces away from the semiconductor layer, and that such differences would result in no unexpected changes in the device of Iida. That is, both the wiring layer locations of Iida and Meister would yield the predictable result of providing an electrically-connective layer in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use a wiring layer located on the side of a first insulator layer that faces away from a semiconductor layer, as taught by Meister, or to use a wiring layer located on the side of a different insulator layer that faces away from a semiconductor layer, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-connective layer in a semiconductor device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Iida/Liu/Meister in view of Yu (US 2016/0049529).
Regarding claim 19, Iida/Liu/Meister shows most aspects of the instant invention (see paragraphs 9-11 and 20-22 above). Iida (see, e.g., fig. 3) further shows that the metal wiring layer M5b comprises a metal isolation frame (separated portions of M5b), and that the metal isolation frame and grating coupler GC have respective orthogonal projections on a carrier substrate. Iida, however, fails to specify that the orthogonal projection of the metal isolation frame surrounds the orthogonal project of the grating coupler on the substrate.
Yu, in the same field of endeavor, teaches that having a metal isolation frame 25/29 surrounding a grating coupler 21, such that the orthogonal projection of the metal isolation frame on a substrate (layer below 30) surrounds the orthogonal projection of the grating coupler on the substrate, can help guide optical transmissions between the grating coupler and the outside (see, e.g., Yu: fig. 13 and par.0050/ll.1-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the orthogonal projection of Iida’s metal isolation frame on Iida’s carrier substrate surrounds the orthogonal projection of Iida’s grating coupler on Iida’s carrier substrate, so as to help guide the optical transmissions between Iida’s grating coupler and the outside.
Allowable Subject Matter
Claims 13-15 are objected to as being dependent upon a rejected base claim but would be allowable if written in independent form including all the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the drawings have been considered but are not found persuasive. The issues the examiner put forth in the previous Office action were not that the features did not have support, but that the drawings failed to properly and distinctly delineate the features from one another, i.e., which portions of a “semiconductor layer” constitute each reference character. In the interest of expediting prosecution, the Office further put forth in the previous Office action the specific and distinct figures in which this lack of delineation between intended features is most obscure or unclear. Beyond generally claiming that the reference characters represent portions of a “semiconductor layer”, the applicant has failed to address the Office’s objections to the specific figures and failed elucidate the delineations between intended features. Accordingly, the objections the drawings put forth in the previous Office action are maintained.
With respect to the claims, the applicants argue:
Iida does not disclose that Iida’s isolating layer BX serves as a channel for transmitting optical signals between the inside and outside of the first insulating layer 212. Therefore, Iida fails to disclose any optical transmission channel that is positioned between the grating coupler and the outside of the semiconductor device for coupling optical signals in or out.
The examiner responds:
The features upon which applicant relies (i.e., a channel for transmitting optical signals between the inside and outside of the first insulating layer 212 [wherein the examiner further notes that element 212 is a feature of the present application and not of Iida]) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As presented in the reply filed by the applicant on 10/14/2025, the claims only state “such that the first insulating layer, instead of the semiconductor material, provides an optical transmission channel to couple optical signals in or out, wherein the optical transmission channel is between the grating coupler and an outside of the semiconductor device that is located on a side, facing away from the semiconductor layer, of the first insulating layer”. Iida shows these aspects of the claimed invention. See, e.g., figure 3 of Iida, wherein the first insulating layer BX, instead of the semiconductor material (e.g., WG1/OR/GC), provides an optical transmission channel (arrow shown between GC and RF2) to couple optical signals in or out (e.g., in or out of layer IF1), wherein the optical transmission channel is between the grating coupler GC and an outside of the semiconductor device RF2 that is located on a side, facing away from the semiconductor layer WG1/OR/GC, of the first insulating layer (see, e.g., pars.0051/ll.1-4 and 0053/ll.14-16).
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights