DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 23 December 2025 is acknowledged.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 21 October 2022 has been considered by the examiner and made of record in the application file.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GLASS CORE INDUCTOR.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 19-22 and 28 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim limitation “a glass substrate comprising means for a glass-core inductor with an inductance density greater than 20 nanohenries per square millimeter” invokes 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Means for the glass core inductor claimed is not provided in the disclosure. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
For the purpose of examination, the claim limitation “...a glass substrate comprising means for a glass-core inductor with an inductance density greater than 20 nanohenries per square millimeter” will be interpreted as “...a glass substrate comprising a glass-core inductor with an inductance density greater than 20 nanohenries per square millimeter”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 11, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Marin et al (US 20220399150 A12, hereinafter “Marin”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”).
Regarding Claim 1 – Marin discloses an apparatus comprising: a glass substrate (202 [0043] and Fig. 3) comprising an inductor (208 [0043] and Fig. 3), the inductor comprising: a plurality of angled through-glass vias (108 [0040-0041] and Fig. 1); and a plurality of traces embedded in the glass substrate (114 [0041] and Fig. 2), wherein individual traces (112 [0041] and Fig. 1) of a plurality of traces extend from one of the plurality of angled through-glass vias to another of the plurality of angled through-glass vias (Fig. 1).
Marin fails to expressly disclose individual angled through-glass vias of the plurality of angled through-glass vias extend from a top surface of the glass substrate to a bottom surface of the glass substrate.
However, Yun discloses individual through-glass vias of the plurality of through-glass vias extend from a top surface of the glass substrate (202A [0026] and Yun Fig. 2B) to a bottom surface of the glass substrate (202B [0026] and Yun Fig. 2B).
Yun discloses an inductor analogous to Marin utilizing a glass core with through-glass vias. Yun teaches that the vias extend completely to the top and bottom of the glass substrate for the benefit of electrically connecting other substrates (Yun [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to combine the teachings of Marin and Yun to extend inductor vias completely to the top and bottom of glass substrate for the benefit of electrically connecting other substrates.
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Regarding Claim 3 – Marin modified by Yun discloses all the limitations of claim 1.
The combination of Marin and Yun further discloses the plurality of angled through-glass vias have a pitch (loop spacing P, Marin [0056] and Fig. 21) greater than the minimum pad diameter, D, plus the minimum pad spacing, S (Marin [0056]). The example given is Dmin = 15 micrometers and Smin = 7 micrometers, for a pitch of 22 micrometers or greater, which overlaps the claimed range of between 80 and 300 micrometers, presenting a prima facie case of obviousness. See MPEP 2144.05(I).
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Regarding Claim 4 – Marin modified by Yun discloses all the limitations of claim 1.
The combination of Marin and Yun further discloses the inductor has inductance density greater than 10 nanohenries per square millimeter, up to 40 nanohenries per square millimeter (Marin [0044]), which overlaps the claimed range of greater than 20 nanohenries per square millimeter, presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Regarding Claim 5 – Marin modified by Yun discloses all the limitations of claim 4.
The combination of Marin and Yun further discloses the inductor has inductance greater than one nanohenry (Examples of Marin Table 1, showing 2.7 and 15.8 nH).
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Regarding Claim 6 – Marin modified by Yun discloses all the limitations of claim 1.
The combination of Marin and Yun further discloses a plurality of pads on the bottom surface of the glass substrate (Yun [0032]), wherein individual pads of the plurality of pads connect two of the angled through-glass vias of the plurality of angled through-glass vias (108a, Marin [0039] and Fig. 1).
Regarding Claim 11 – Marin discloses an apparatus comprising: a glass substrate (202 [0043] and Fig. 3) comprising an inductor (208 [0043] and Fig. 3), the inductor comprising a plurality of inductor turns ([0003] and Fig. 1), wherein individual inductor turns of the plurality of inductor turns comprise: a first conductor (108b [0039] and Fig. 1) extending through the glass substrate (Fig. 1), wherein the first conductor is angled at least ten degrees relative to a line normal to the top surface of the glass substrate (interior angle between 108B and 108C may be between 30° and 120° [0041]); a second conductor (108b [0039] and Fig. 1) extending through the glass substrate (Fig. 1), wherein the second conductor is angled at least ten degrees relative to the line normal to the top surface of the glass substrate (interior angle between 108B and 108C may be between 30° and 120° [0041]), wherein the second conductor is electrically coupled to the first conductor (at 108a [0039] and Fig. 1); and a third conductor extending along the top surface of the glass substrate (112 [0041] and Fig. 1), wherein the third conductor is electrically coupled to the second conductor and an adjacent inductor turn of the inductor (Fig. 1).
Marin fails to expressly disclose the first and second conductors extend from a top surface of the glass substrate to a bottom surface of the glass substrate.
However, Yun discloses the first and second conductors extend from a top surface of the glass substrate (202A [0026] and Yun Fig. 2B) to a bottom surface of the glass substrate (202B [0026] and Yun Fig. 2B).
Yun discloses an inductor analogous to Marin utilizing a glass core with through-glass vias. Yun teaches that the conductors extend completely to the top and bottom of the glass substrate for the benefit of electrically connecting other substrates (Yun [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to combine the teachings of Marin and Yun to extend inductor conductors completely to the top and bottom of glass substrate for the benefit of electrically connecting other substrates.
Regarding Claim 13 – Marin modified by Yun discloses all the limitations of claim 11.
The combination of Marin and Yun further discloses a distance between the first conductor and the second conductor of individual inductor turns of the plurality of inductor turns at the top surface (loop spacing P, Marin [0056] and Fig. 21) is greater than the minimum pad diameter, D, plus the minimum pad spacing, S (Marin [0056]). The example given is Dmin = 15 micrometers and Smin = 7 micrometers, for a pitch of 22 micrometers or greater, which overlaps the claimed range of between 80 and 300 micrometers, presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Regarding Claim 14 – Marin modified by Yun discloses all the limitations of claim 11.
The combination of Marin and Yun further discloses the inductor has inductance density greater than 10 nanohenries per square millimeter, up to 40 nanohenries per square millimeter (Marin [0044]), which overlaps the claimed range of greater than 20 nanohenries per square millimeter, presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Regarding Claim 15 – Marin modified by Yun discloses all the limitations of claim 14.
The combination of Marin and Yun further discloses the inductor has inductance greater than one nanohenry (Examples of Marin Table 1, showing 2.7 and 15.8 nH).
Regarding Claim 16 – Marin modified by Yun discloses all the limitations of claim 11.
The combination of Marin and Yun further discloses a plurality of pads on the bottom surface of the glass substrate (Yun [0032]), wherein individual pads (108a, Marin [0039] and Fig. 1) of the plurality of pads connect the first conductor to the second conductor of individual inductor turns of the plurality of inductor turns (Fig. 1).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Marin et al (US 20220399150 A12, hereinafter “Marin”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Ecton et al (US 20200105685 A1, hereinafter “Ecton”).
Regarding Claim 2 – Marin modified by Yun discloses all the limitations of claim 1.
The combination of Marin and Yun further discloses the apparatus comprises an integrated circuit component (310, Marin [0045] and Fig. 4, wherein the integrated circuit component comprises the glass substrate (312, Marin [0045] and Fig. 4)
The combination of Marin and Yun fails to expressly disclose the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor.
However, Ecton discloses the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor (Ecton [0033].
Ecton discloses an inductor without a magnetic core analogous to Marin. Ecton teaches integrating an air core inductor (ACI) with a FIVR for lower inductor DC resistance and higher regulator efficiency (Ecton [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin in Ecton to integrate and FIVR with a magnetic-free core inductor for the benefit of lower inductor DC resistance and higher regulator efficiency.
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Regarding Claim 12 – Marin modified by Yun discloses all the limitations of claim 11.
The combination of Marin and Yun further discloses the apparatus comprises an integrated circuit component (310, Marin [0045] and Fig. 4, wherein the integrated circuit component comprises the glass substrate (312, Marin [0045] and Fig. 4)
The combination of Marin and Yun fails to expressly disclose the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor.
However, Ecton discloses the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor (Ecton [0033].
Ecton discloses an inductor without a magnetic core analogous to Marin. Ecton teaches integrating an air core inductor (ACI) with a FIVR for lower inductor DC resistance and higher regulator efficiency (Ecton [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin in Ecton to integrate and FIVR with an air core inductor for the benefit of lower inductor DC resistance and higher regulator efficiency.
Claims 7-9, 17-18, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Marin et al (US 20220399150 A12, hereinafter “Marin”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Bharath et al (US 20200066830 A1, hereinafter “Bharath”).
Regarding Claim 7 – Marin modified by Yun discloses all the limitations of claim 1.
The combination of Marin and Yun fails to disclose: a first plurality of build-up layers adjacent the top surface of the glass substrate; a second plurality of build-up layers adjacent the bottom surface of the glass substrate; and a semiconductor die adjacent the first plurality of build-up layers.
However, Bharath discloses: a first plurality of build-up layers adjacent the top surface of the glass substrate (106, 113, 114, 116, 117, 112, and 120 on top, Bharath [0051] and Fig. 2A); a second plurality of build-up layers adjacent the bottom surface of the glass substrate (118, 119, 106, and 101 on bottom, Bharath [0109] and Fig. 2A); and a semiconductor die adjacent the first plurality of build-up layers (110, Bharath [0051] and Fig. 2A).
Bharath discloses an analogous inductor to Marin with a glass core. Bharath teaches a build-up of layers under a semiconductor die containing a FIVR circuit for the benefits of space saving and lower power conversion losses (Bharath [0029]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin and Bharath to connect a semiconductor die to a glass core inductor using a buildup of layers for the benefits of space saving and lower power conversion losses.
Regarding Claim 8 – Marin modified by Yun and Bharath discloses all the limitations of claim 7.
The combination of Marin, Yun, and Bharath further discloses the semiconductor die is a processor die (Bharath [0058]).
Regarding Claim 9 – Marin modified by Yun and Bharath discloses all the limitations of claim 7.
The combination of Marin, Yun, and Bharath further discloses the semiconductor die is a memory die (Bharath describes the chip position as described above, and Marin teaches the disclosed implementation can include a memory die, Marin [0057]).
Regarding Claim 17 – Marin modified by Yun discloses all the limitations of claim 11.
The combination of Marin and Yun fails to disclose: a first plurality of build-up layers adjacent the top surface of the glass substrate; a second plurality of build-up layers adjacent the bottom surface of the glass substrate; and a semiconductor die adjacent the first plurality of build-up layers.
However, Bharath discloses: a first plurality of build-up layers adjacent the top surface of the glass substrate (106, 113, 114, 116, 117, 112, and 120 on top, Bharath [0051] and Fig. 2A); a second plurality of build-up layers adjacent the bottom surface of the glass substrate (118, 119, 106, and 101 on bottom, Bharath [0109] and Fig. 2A); and a semiconductor die adjacent the first plurality of build-up layers (110, Bharath [0051] and Fig. 2A).
Bharath discloses an analogous inductor to Marin with a glass core. Bharath teaches a build-up of layers under a semiconductor die containing a FIVR circuit for the benefits of space saving and lower power conversion losses (Bharath [0029]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin and Bharath to connect a semiconductor die to a glass core inductor using a buildup of layers for the benefits of space saving and lower power conversion losses.
Regarding Claim 18 – Marin modified by Yun and Bharath discloses all the limitations of claim 17.
The combination of Marin, Yun, and Bharath further discloses the semiconductor die is a processor die (Bharath [0058]).
Regarding Claim 26 – Marin modified by Yun and Bharath discloses all the limitations of claim 17.
The combination of Marin, Yun, and Bharath further discloses the semiconductor die is a memory die (Bharath describes the chip position as described above, and Marin teaches the disclosed implementation can include a memory die, Marin [0057]).
Claims 19, 21-22, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Marin et al (US 20220399150 A12, hereinafter “Marin”), in view of Bharath et al (US 20200066830 A1, hereinafter “Bharath”).
Regarding Claim 19 – Marin discloses an apparatus comprising: a glass substrate comprising a glass-core inductor with an inductance density greater than 20 nanohenries per square millimeter (greater than 10 nanohenries per square millimeter, up to 40 nanohenries per square millimeter, Marin [0044]).
Marin fails to disclose a first plurality of build-up layers adjacent a top surface of the glass substrate; and a second plurality of build-up layers adjacent a bottom surface of the glass substrate.
However, Bharath discloses a first plurality of build-up layers adjacent a top surface of the glass substrate (106, 113, 114, 116, 117, 112, and 120 on top, Bharath [0051] and Fig. 2A); and a second plurality of build-up layers adjacent a bottom surface of the glass substrate (118, 119, 106, and 101 on bottom, Bharath [0109] and Fig. 2A).
Bharath discloses an analogous inductor to Marin with a glass core. Bharath teaches a build-up of layers under a semiconductor die containing a FIVR circuit for the benefits of space saving and lower power conversion losses (Bharath [0029]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin and Bharath to connect a semiconductor die to a glass core inductor using a buildup of layers for the benefits of space saving and lower power conversion losses.
Regarding Claim 21 – Marin modified by Bharath discloses all the limitations of claim 19.
The combination of Marin and Bharath further discloses the inductor has inductance density greater than 10 nanohenries per square millimeter, up to 40 nanohenries per square millimeter (Marin [0044]), which overlaps the claimed range of greater than 20 nanohenries per square millimeter, presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Regarding Claim 22 – Marin modified by Bharath discloses all the limitations of claim 21.
The combination of Marin and Bharath further discloses the inductor has inductance greater than one nanohenry (Examples of Marin Table 1, showing 2.7 and 15.8 nH).
Regarding Claim 28 – Marin modified by Bharath discloses all the limitations of claim 19.
The combination of Marin and Bharath further discloses the glass-core inductor comprises a plurality of inductor turns (Marin [0044]), wherein the plurality of inductor turns have a pitch (loop spacing P, Marin [0056] and Fig. 21) greater than the minimum pad diameter, D, plus the minimum pad spacing, S (Marin [0056]). The example given is Dmin = 15 micrometers and Smin = 7 micrometers, for a pitch of 22 micrometers or greater, which overlaps the claimed range of between 80 and 300 micrometers, presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Claims 10 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Marin et al (US 20220399150 A12, hereinafter “Marin”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Berdy et al (US 20160020013 A1, hereinafter “Berdy”).
Regarding Claim 10 – Marin modified by Yun discloses all the limitations of claim 1.
The combination of Marin and Yun discloses the glass substrate (202 [0043] and Fig. 3) comprises an inductor (208 [0043] and Fig. 3), the inductor comprising: a plurality of angled through-glass vias (108 [0040-0041], wherein individual angled through-glass vias of the plurality of angled through-glass vias extend from the top surface of the glass substrate (202A [0026] and Yun Fig. 2B) to the bottom surface of the glass substrate (202B [0026] and Yun Fig. 2B); and a plurality of traces on the top surface of the glass substrate (207, Yun [0027] and annotated Fig. 2B), wherein individual traces (112 [0041] and Fig. 1) of a plurality of traces extend from one of the plurality of angled through-glass vias to another of the plurality of angled through-glass vias (Fig. 1).
The combination of Marin and Yun fails to disclose a second inductor comprising a second plurality of vias, wherein individual vias of the second plurality of vias extend from the top surface of the substrate to the bottom surface of the substrate; and a second plurality of traces on the top surface of the glass substrate, wherein individual traces of the second plurality of traces extend from one of the second plurality of vias to another of the second plurality of vias.
However, Berdy discloses a second inductor (404, Berdy [0006] and Fig. 4A) comprising a second plurality of vias (412, Berdy [0061] and Fig. 4D), wherein individual vias of the second plurality of vias extend from the top surface of the substrate to the bottom surface of the substrate (Berdy Fig. 4D); and a second plurality of traces on the top surface of the glass substrate (414-1 and 414-2, Berdy [0061] and Fig. 4A), wherein individual traces of the second plurality of traces extend from one of the second plurality of vias to another of the second plurality of vias (Berdy Fig. 4A).
Like Marin, Berdy discloses a 3-D inductor. Berdy teaches first and second inductors to filter current spikes from rapidly switching loads (Berdy [0002]). Therefore, it would’ve been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin and Berdy to include a second inductor for the benefit of filtering current spikes from rapidly switching loads.
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Regarding Claim 27 – Marin modified by Yun discloses all the limitations of claim 11.
The combination of Marin and Yun discloses the glass substrate (202 [0043] and Fig. 3) comprising an inductor (208 [0043] and Fig. 3), the inductor comprising a plurality of inductor turns ([0003] and Fig. 1), wherein individual inductor turns of the plurality of inductor turns comprise: a first conductor (108b [0039] and Fig. 1) extending from the top surface of the glass substrate to the bottom surface of the glass substrate (202A and 202B, Yun [0026] and Fig. 2B), wherein the first conductor is angled at least ten degrees relative to a line normal to the top surface of the glass substrate (interior angle between 108B and 108C may be between 30° and 120° [0041]); a second conductor (108b [0039] and Fig. 1) extending through the glass substrate (Fig. 1), wherein the second conductor is angled at least ten degrees relative to the line normal to the top surface of the glass substrate (interior angle between 108B and 108C may be between 30° and 120° [0041]), wherein the second conductor is electrically coupled to the first conductor (at 108a [0039] and Fig. 1); and a third conductor extending along the top surface of the glass substrate (112 [0041] and Fig. 1), wherein the third conductor is electrically coupled to the second conductor and an adjacent inductor turn of the inductor (Fig. 1).
The combination of Marin and Yun fails to disclose a second inductor comprising a second plurality of inductor turns, wherein individual inductor turns of the second plurality of inductor turns extend from the top surface of the substrate to the bottom surface of the substrate.
However, Berdy discloses a second inductor (404, Berdy [0006] and Fig. 4A) comprising a second plurality of inductor turns (412, Berdy [0061] and Fig. 4D), wherein individual inductor turns of the second plurality of inductor turns extend from the top surface of the substrate to the bottom surface of the substrate (Berdy Fig. 4D).
Like Marin, Berdy discloses a 3-D inductor. Berdy teaches first and second inductors to filter current spikes from rapidly switching loads (Berdy [0002]). Therefore, it would’ve been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin and Berdy to include a second inductor for the benefit of filtering current spikes from rapidly switching loads.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Marin et al (US 20220399150 A12, hereinafter “Marin”), in view of Bharath et al (US 20200066830 A1, hereinafter “Bharath”), and further in view of Ecton et al (US 20200105685 A1, hereinafter “Ecton”).
Regarding Claim 20 – Marin modified by Bharath discloses all the limitations of claim 19.
The combination of Marin and Bharath further discloses the apparatus comprises an integrated circuit component (310, Marin [0045] and Fig. 4), wherein the integrated circuit component comprises the glass substrate (312, Marin [0045] and Fig. 4)
The combination of Marin and Bharath fails to expressly disclose the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor.
However, Ecton discloses the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor (Ecton [0033].
Ecton discloses an inductor without a magnetic core analogous to Marin. Ecton teaches integrating an air core inductor (ACI) with a FIVR for lower inductor DC resistance and higher regulator efficiency (Ecton [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Marin in Ecton to integrate and FIVR with a magnetic-free inductor for the benefit of lower inductor DC resistance and higher regulator efficiency.
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Second Set of 35 USC 103 Rejections:
Claims 1, 6, 10-11, 16, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi et al (US 20240222353 A12, hereinafter “Higuchi”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”).
Regarding Claim 1 – Higuchi discloses an apparatus comprising: a glass substrate (11 [0037] and Fig. 11) comprising an inductor (20 [0157] and Fig. 8), the inductor comprising: a plurality of angled through-glass vias (21 [0158] and Fig. 11), wherein individual angled through-glass vias of the plurality of angled through-glass vias extend from a top surface of the glass substrate (Fig. 11); and a plurality of traces on a top surface of the glass substrate (22 [0158] and Fig. 11), wherein individual traces of a plurality of traces extend from one of the plurality of angled through-glass vias to another of the plurality of angled through-glass vias ([0167] and Fig. 9).
Higuchi fails to expressly disclose individual angled through-glass vias of the plurality of angled through-glass vias extend to a bottom surface of the glass substrate.
However, Yun discloses individual through-glass vias of the plurality of through-glass vias extend to a bottom surface of the glass substrate (202B [0026] and Yun Fig. 2B).
Yun discloses an inductor analogous to Higuchi utilizing a non-magnetic core with through-glass vias. Yun teaches that the vias extend completely to the top and bottom of the glass substrate for the benefit of electrically connecting other substrates (Yun [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to combine the teachings of Higuchi and Yun to extend inductor vias completely to the top and bottom of glass substrate for the benefit of electrically connecting other substrates.
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Regarding Claim 6 – Higuchi modified by Yun discloses all the limitations of claim 1.
The combination of Higuchi and Yun further discloses a plurality of pads on the bottom surface of the glass substrate (Yun [0032]), wherein individual pads of the plurality of pads (2133, Higuchi [0162]) connect two of the angled through-glass vias of the plurality of angled through-glass vias (Fig. 11).
Regarding Claim 10 – Higuchi modified by Yun discloses all the limitations of claim 1.
The combination of Higuchi and Yun discloses the glass substrate (11, Higuchi [0037] and Fig. 8) comprises a second inductor (30, Higuchi [0157] and Fig. 8), the second inductor comprising: a second plurality of angled through-glass vias (combination of each length of 3131 and 3132, Higuchi [0175] and Fig. 9), wherein individual angled through-glass vias of the second plurality of angled through-glass vias extend from the top surface of the glass substrate (202A, Yun [0026] and Fig. 2B) to the bottom surface of the glass substrate (202B, Yun [0026] and Fig. 2B); and a second plurality of traces on the top surface of the glass substrate (32, Higuchi [0171] and Fig. 8), wherein individual traces of a second plurality of traces extend from one of the second plurality of angled through-glass vias to another of the second plurality of angled through-glass vias (Higuchi [0178] and Fig. 9).
Regarding Claim 11 – Higuchi discloses an apparatus comprising: a glass substrate (11 [0037] and Fig. 11) comprising an inductor (20 [0157] and Fig. 8), the inductor comprising a plurality of inductor turns (combination of each length of 21 and 22 [0158] and Fig. 11), wherein individual inductor turns of the plurality of inductor turns comprise: a first conductor (2131 [0162] and Fig. 11) extending through the glass substrate (Fig. 11), wherein the first conductor is angled at least ten degrees relative to a line normal to the top surface of the glass substrate (90° - 54.7° = 35.3° [0156] and Fig. 11); a second conductor (2132 [0162] and Fig. 11) extending through the glass substrate (Fig. 11), wherein the second conductor is angled at least ten degrees relative to the line normal to the top surface of the glass substrate (90° - 54.7° = 35.3° [0156] and Fig. 11), wherein the second conductor is electrically coupled to the first conductor (2133 [0162] and Fig. 11); and a third conductor extending along the top surface of the glass substrate (22 [0158] and Fig. 11), wherein the third conductor is electrically coupled to the second conductor and an adjacent inductor turn of the inductor ([0167] and Fig. 9).
Higuchi fails to expressly disclose the first and second conductors extend from a top surface of the glass substrate to a bottom surface of the glass substrate.
However, Yun discloses the first and second conductors extend from a top surface of the glass substrate (202A [0026] and Yun Fig. 2B) to a bottom surface of the glass substrate (202B [0026] and Yun Fig. 2B).
Yun discloses an inductor analogous to Higuchi utilizing a glass core with through-glass vias. Yun teaches that the conductors extend completely to the top and bottom of the glass substrate for the benefit of electrically connecting other substrates (Yun [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to combine the teachings of Higuchi and Yun to extend inductor conductors completely to the top and bottom of glass substrate for the benefit of electrically connecting other substrates.
Regarding Claim 16 – Higuchi modified by Yun discloses all the limitations of claim 11.
The combination of Higuchi and Yun further discloses a plurality of pads on the bottom surface of the glass substrate (Yun [0032]), wherein individual pads of the plurality of pads (2133, Higuchi [0162]) connect the first conductor to the second conductor of individual inductor turns of the plurality of inductor turns (Fig. 11).
Regarding Claim 27 – Higuchi modified by Yun discloses all the limitations of claim 11.
The combination of Higuchi and Yun further discloses the glass substrate (11, Higuchi [0037] and Fig. 8) comprises a second inductor (30, Higuchi [0157] and Fig. 8), the second inductor comprising a second plurality of inductor turns (combination of each length of 31 and 32, Higuchi [0158] and Fig. 8), wherein individual inductor turns of the second plurality of inductor turns comprise: a first conductor (3131 [0175] and Fig. 9) extending from the top surface of the glass substrate to the bottom surface of the glass substrate (202A and 202B, Yun [0026] and Fig. 2B), wherein the first conductor is angled at least ten degrees relative to a line normal to the top surface of the glass substrate (90° - 54.7° = 35.3° [0156]); a second conductor (3132 [0175] and Fig. 9) extending through the glass substrate (Fig. 11), wherein the second conductor is angled at least ten degrees relative to the line normal to the top surface of the glass substrate (90° - 54.7° = 35.3° [0156]), wherein the second conductor is electrically coupled to the first conductor (3133 [0175] and Fig. 9); and a third conductor extending along the top surface of the glass substrate (32 [0171] and Fig. 8), wherein the third conductor is electrically coupled to the second conductor and an adjacent inductor turn of the inductor ([0178] and Fig. 9).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi et al (US 20240222353 A12, hereinafter “Higuchi”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Ecton et al (US 20200105685 A1, hereinafter “Ecton”).
Regarding Claim 2 – Higuchi modified by Yun discloses all the limitations of claim 1.
The combination of Higuchi and Yun further discloses the apparatus comprises an integrated circuit component (A1, Higuchi [0098] and annotated Fig. 7), wherein the integrated circuit component comprises the glass substrate (10, Higuchi [0106] and Fig. 7).
The combination of Higuchi and Yun fails to expressly disclose the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor.
However, Ecton discloses the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor (Ecton [0033].
Ecton discloses an inductor without a magnetic core analogous to Higuchi. Ecton teaches integrating an air core inductor (ACI) with a FIVR for lower inductor DC resistance and higher regulator efficiency (Ecton [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi in Ecton to integrate and FIVR with a magnetic-free core inductor for the benefit of lower inductor DC resistance and higher regulator efficiency.
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Regarding Claim 12 – Higuchi modified by Yun discloses all the limitations of claim 11.
The combination of Higuchi and Yun further discloses the apparatus comprises an integrated circuit component (A1, Higuchi [0098] and annotated Fig. 7), wherein the integrated circuit component comprises the glass substrate (10, Higuchi [0106] and Fig. 7)
The combination of Higuchi and Yun fails to expressly disclose the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor.
However, Ecton discloses the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor (Ecton [0033].
Ecton discloses an inductor without a magnetic core analogous to Higuchi. Ecton teaches integrating an air core inductor (ACI) with a FIVR for lower inductor DC resistance and higher regulator efficiency (Ecton [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi in Ecton to integrate and FIVR with a magnetic-free core inductor for the benefit of lower inductor DC resistance and higher regulator efficiency.
Claims 3, 7-9, 13, 17-18, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi et al (US 20240222353 A12, hereinafter “Higuchi”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Bharath et al (US 20200066830 A1, hereinafter “Bharath”).
Regarding Claim 3 – Higuchi modified by Yun discloses all the limitations of claim 1.
The combination of Higuchi and Yun fails to disclose the plurality of angled through-glass vias have a pitch between 80 and 300 micrometers.
However, Bharath discloses the pitch from one inductor loop to the next can be in the range of 100-250 or 300-400 microns (Bharath 0035]), overlapping the claimed range and presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Bharath discloses an analogous inductor to Higuchi with a non-magnetic core. Bharath teaches setting the inductor loop pitch at least equal to the diameter of the inductor conductors to give some separation between loops (Bharath [0035]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi and Bharath to set the inductor loop pitch at least equal to the diameter of the inductor conductors to give some separation between loops.
Regarding Claim 7 – Higuchi modified by Yun discloses all the limitations of claim 1.
The combination of Higuchi and Yun fails to disclose: a first plurality of build-up layers adjacent the top surface of the glass substrate; a second plurality of build-up layers adjacent the bottom surface of the glass substrate; and a semiconductor die adjacent the first plurality of build-up layers.
However, Bharath discloses: a first plurality of build-up layers adjacent the top surface of the glass substrate (106, 113, 114, 116, 117, 112, and 120 on top, Bharath [0051] and Fig. 2A); a second plurality of build-up layers adjacent the bottom surface of the glass substrate (118, 119, 106, and 101 on bottom, Bharath [0109] and Fig. 2A); and a semiconductor die adjacent the first plurality of build-up layers (110, Bharath [0051] and Fig. 2A).
Bharath discloses an analogous inductor to Higuchi. Bharath teaches a build-up of layers under a semiconductor die containing a FIVR circuit for the benefits of space saving and lower power conversion losses (Bharath [0029]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi and Bharath to connect a semiconductor die to a glass core inductor using a buildup of layers for the benefits of space saving and lower power conversion losses.
Regarding Claim 8 – Higuchi modified by Yun and Bharath discloses all the limitations of claim 7.
The combination of Higuchi, Yun, and Bharath further discloses the semiconductor die is a processor die (Bharath [0058]).
Regarding Claim 9 – Higuchi modified by Yun and Bharath discloses all the limitations of claim 7.
The combination of Higuchi, Yun, and Bharath further discloses the semiconductor die is a memory die (Bharath describes the chip position as described above, and Yun teaches the disclosed implementation can include a memory die, 632, Yun [0059]).
Regarding Claim 13 – Higuchi modified by Yun discloses all the limitations of claim 11.
The combination of Higuchi and Yun fails to disclose the plurality of angled through-glass vias have a pitch between 80 and 300 micrometers.
However, Bharath discloses the pitch from one inductor loop to the next can be in the range of 100-250 or 300-400 microns (Bharath 0035]), overlapping the claimed range and presenting a prima facie case of obviousness. See MPEP 2144.05(I).
Bharath discloses an analogous inductor to Higuchi with a non-magnetic core. Bharath teaches setting the inductor loop pitch at least equal to the diameter of the inductor conductors to give some separation between loops (Bharath [0035]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi and Bharath to set the inductor loop pitch at least equal to the diameter of the inductor conductors to give some separation between loops.
Regarding Claim 17 – Higuchi modified by Yun discloses all the limitations of claim 11.
The combination of Higuchi and Yun fails to disclose: a first plurality of build-up layers adjacent the top surface of the glass substrate; a second plurality of build-up layers adjacent the bottom surface of the glass substrate; and a semiconductor die adjacent the first plurality of build-up layers.
However, Bharath discloses: a first plurality of build-up layers adjacent the top surface of the glass substrate (106, 113, 114, 116, 117, 112, and 120 on top, Bharath [0051] and Fig. 2A); a second plurality of build-up layers adjacent the bottom surface of the glass substrate (118, 119, 106, and 101 on bottom, Bharath [0109] and Fig. 2A); and a semiconductor die adjacent the first plurality of build-up layers (110, Bharath [0051] and Fig. 2A).
Bharath discloses an analogous inductor to Higuchi. Bharath teaches a build-up of layers under a semiconductor die containing a FIVR circuit for the benefits of space saving and lower power conversion losses (Bharath [0029]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi and Bharath to connect a semiconductor die to a glass core inductor using a buildup of layers for the benefits of space saving and lower power conversion losses.
Regarding Claim 18 – Higuchi modified by Yun and Bharath discloses all the limitations of claim 17.
The combination of Higuchi, Yun, and Bharath further discloses the semiconductor die is a processor die (Bharath [0058]).
Regarding Claim 26 – Higuchi modified by Yun and Bharath discloses all the limitations of claim 17.
The combination of Higuchi, Yun, and Bharath further discloses the semiconductor die is a memory die (Bharath describes the chip position as described above, and Yun teaches the disclosed implementation can include a memory die, 632 [0059]).
Claims 4-5, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi et al (US 20240222353 A12, hereinafter “Higuchi”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Duevel et al (US 20140027880 A1, hereinafter “Duevel”).
Regarding Claim 4 – Higuchi modified by Yun discloses all the limitations of claim 1.
The combination of Higuchi and Yun fails to disclose the inductor has inductance density greater than 20 nanohenries per square millimeter.
However, Duevel discloses the inductor has inductance density greater than 20 nanohenries per square millimeter (252 nH/mm2, Duevel [0054]).
Duevel discloses an inductor with a non-magnetic core analogous to Higuchi. Duevel teaches the inductance per unit area can be more than an order of magnitude above the claimed inductance per unit area (Duevel [0054]), allowing for inductors greater than 1 nH to fit in a space smaller than 50 by 100 microns (Duevel [0049]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi and Duevel with an inductance greater than 20 nanohenries per square millimeter, for the benefit of making inductors greater than 1 nH in an area smaller than 50 by 100 microns.
Regarding Claim 5 – Higuchi modified by Yun discloses all the limitations of claim 4.
The combination of Higuchi and Yun fails to disclose the inductor has inductance greater than one nanohenry.
However, Duevel discloses an inductor with inductance of 0.63 nH. Using the disclosed structure for an inductor of greater than one nanohenry is a matter scaling by routine optimization, and therefore presents a prima facie case of obviousness. See MPEP 2144.05(II).
Regarding Claim 14 – Higuchi modified by Yun discloses all the limitations of claim 11.
The combination of Higuchi and Yun fails to disclose the inductor has inductance density greater than 20 nanohenries per square millimeter.
However, Duevel discloses the inductor has inductance density greater than 20 nanohenries per square millimeter (252 nH/mm2, Duevel [0054]).
Duevel discloses an inductor with a non-magnetic core analogous to Higuchi. Duevel teaches the inductance per unit area can be more than an order of magnitude above the claimed inductance per unit area (Duevel [0054]), allowing for inductors greater than 1 nH to fit in a space smaller than 50 by 100 microns (Duevel [0049]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi and Duevel with an inductance greater than 20 nanohenries per square millimeter, for the benefit of making inductors greater than 1 nH in an area smaller than 50 by 100 microns.
Regarding Claim 15 – Higuchi modified by Yun discloses all the limitations of claim 14.
The combination of Higuchi and Yun fails to disclose the inductor has inductance greater than one nanohenry.
However, Duevel discloses an inductor with inductance of 0.63 nH. Using the disclosed structure for an inductor of greater than one nanohenry is a matter scaling by routine optimization, and therefore presents a prima facie case of obviousness. See MPEP 2144.05(II).
Claims 19, 21-22, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Bharath et al (US 20200066830 A1, hereinafter “Bharath”), in view of Duevel et al (US 20140027880 A1, hereinafter “Duevel”).
Regarding Claim 19 – Bharath discloses an apparatus comprising: a glass substrate ([0046]); a first plurality of build-up layers adjacent a top surface of the glass substrate (106, 113, 114, 116, 117, 112, and 120 on top, Bharath [0051] and Fig. 2A); and a second plurality of build-up layers adjacent a bottom surface of the glass substrate (118, 119, 106, and 101 on bottom, Bharath [0109] and Fig. 2A).
Bharath fails to disclose a glass-core inductor with an inductance density greater than 20 nanohenries per square millimeter.
However, Duevel discloses a glass-core inductor with an inductance density greater than 20 nanohenries per square millimeter (252 nH/mm2, Duevel [0054]).
Duevel discloses an inductor analogous to Bharath. Duevel teaches the inductance per unit area can be more than an order of magnitude above the claimed inductance per unit area (Duevel [0054]), allowing for an inductor of 0.6 nH to fit in 50 by 50 microns (Duevel [0049]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bharath and Duevel with an inductance greater than 20 nanohenries per square millimeter, for the benefit of making an inductor of 0.6 nH to fit in 50 by 50 microns.
Regarding Claim 21 – Bharath modified by Duevel discloses all the limitations of claim 19.
The combination of Bharath and Duevel further discloses the glass-core inductor has inductance density greater than 20 nanohenries per square millimeter (252 nH/mm2, Duevel [0054]).
Regarding Claim 22 – Bharath modified by Duevel discloses all the limitations of claim 21.
The combination of Bharath and Duevel further discloses the inductor has inductance greater than one nanohenry (e.g. Bharath [0063] at 2 nH, and whereas Bharath states air-core integrated inductors integrated into package dielectric material have an inductance less than 1 nH, scaling can be performed as a matter of routine optimization. See MPEP 2144.05(II)).
Regarding Claim 28 – Bharath modified by Duevel discloses all the limitations of claim 19.
The combination of Bharath and Duevel further discloses the glass-core inductor comprises a plurality of inductor turns (Bharath [0052]), wherein the plurality of inductor turns have a pitch between 80 and 300 micrometers (can be in the range of 100-250 or 300-400 microns (Bharath [0035]), overlapping the claimed range and presenting a prima facie case of obviousness. See MPEP 2144.05(I).)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi et al (US 20240222353 A12, hereinafter “Higuchi”), in view of Yun et al (US 20200020473 A1, hereinafter “Yun”), and further in view of Bharath et al (US 20200066830 A1, hereinafter “Bharath”), and further in view of Ecton et al (US 20200105685 A1, hereinafter “Ecton”).
Regarding Claim 20 – Higuchi modified by Yun and Bharath discloses all the limitations of claim 19.
The combination of Higuchi, Yun, and Bharath further discloses the apparatus comprises an integrated circuit component (A1, Higuchi [0098] and annotated Fig. 7), wherein the integrated circuit component comprises the glass substrate (10, Higuchi [0106] and Fig. 7).
The combination of Higuchi, Yun, and Bharath fails to expressly disclose the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor.
However, Ecton discloses the integrated circuit component comprises a fully-integrated voltage regulator (FIVR), wherein the FIVR comprises the inductor (Ecton [0033].
Ecton discloses an inductor without a magnetic core analogous to Higuchi. Ecton teaches integrating an air core inductor (ACI) with a FIVR for lower inductor DC resistance and higher regulator efficiency (Ecton [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Higuchi in Ecton to integrate and FIVR with a magnetic-free inductor for the benefit of lower inductor DC resistance and higher regulator efficiency.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898