DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 12/19/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 14-17, 21-23, 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al (US Publication No. 2022/0013410).
Regarding claim 1, You discloses an integrated circuit comprising: a first semiconductor body Fig 2, 212 extending lengthwise in a first direction between a first source region and a first drain region Fig 2 and Fig 16;a second semiconductor body Fig 2, 212 extending lengthwise in the first direction between a second source region and a second drain region Fig 2 and Fig 16;a gate structure Fig 14, 1202 extending in a second direction different from the first direction Fig 14 and Fig 16, the gate structure including a first gate layer across the first semiconductor body and a second gate layer across the second semiconductor body Fig 14; and a dielectric wall Fig 12, 1002/1004 and Fig 25A, 1002/1004/2402 extending in the first direction between the first and second source regions Fig 12-Fig 16,the first and second drain regions, and the first and second gate layers Fig 16-17.
Regarding claim 2, You discloses wherein the dielectric wall comprises silicon and nitrogen, or silicon and oxygen ¶0031.
Regarding claim 3, You discloses wherein the dielectric wall extends in the first direction between additional adjacent source or drain regions of additional semiconductor devices Fig 16-17 and Fig 20A-20B.
Regarding claim 5, You discloses spacer structures on sidewalls of each of the first and second gate layers, wherein a dielectric material of the spacer structures is a same dielectric material as the dielectric wall ¶0031 and 0035.
Regarding claim 6, You discloses wherein the dielectric wall is a first dielectric wall, and there is substantially equal spacing in the second direction between the first dielectric wall and a second dielectric wall to a first side of the first dielectric wall, and in the second direction between the first dielectric wall and a third dielectric wall to a second side of the first dielectric wall Fig 8-19 and Fig 20A-20B.
Regarding claim 14, You discloses an integrated circuit comprising: a first semiconductor body Fig 2, 212 extending in a first direction from a first side of a first source or drain region Fig 2, Fig 16 and Fig 20A;a second semiconductor body Fig 2, 212 extending in the first direction from a second side of the first source or drain region Fig 2, Fig 16 and Fig 20A;a third semiconductor body Fig 2, 212 extending in the first direction from a first side of a second source or drain region Fig 2, Fig 16 and Fig 20A;a fourth semiconductor body Fig 2, 212 extending in the first direction from a second side of the second source or drain region Fig 2, Fig 16 and Fig 20A;a first gate structure Fig 14, 1202 extending across the first semiconductor body in a second direction different from the first direction Fig 2, Fig 16-17 and Fig 20A;a second gate structure Fig 14, 1202 extending across the second semiconductor body in the second direction; a third gate structure extending across the third semiconductor body in the second direction ¶0058;a fourth gate structure extending across the fourth semiconductor body in the second direction¶0058; and a dielectric wall Fig 25A and 26A, 1002/1004/2402 extending in the first direction between the first gate structure and the third gate structure, between the first source or drain region and the second source or drain region, and between the second gate structure and the fourth gate structure¶0058.
Regarding claim 15, You discloses wherein the first gate structure extends colinear with the third gate structure in the second direction, and the second gate structure extends colinear with the fourth gate structure in the second direction Fig 16-17, Fig 20A-20B and Fig 25A-26B.
Regarding claim 16, You discloses a gate dielectric layer around the first, second, third, and fourth semiconductor bodies Fig 20A ¶0044.
Regarding claim 17, You discloses, wherein the gate dielectric layer is not present on sidewalls of the dielectric wall as it extends between the first gate structure and the third gate structure and between the second gate structure and the fourth gate structure Fig 16-17, Fig 20A-20B and Fig 25A-26B.
.
Regarding claim 21, You discloses an integrated circuit comprising:a plurality of semiconductor devices having one or more semiconductor bodies Fig 2, 212 extending lengthwise in a first direction between corresponding source or drain regions Fig 2, Fig 16 and Fig 20A;a plurality of gate layers Fig 16, 1202 , each gate layer of the plurality of gate layers extending in a second direction different from the first direction across the one or more semiconductor bodies of a given semiconductor device of the plurality of semiconductor devices Fig 16-17, Fig 20A-20B and Fig 25A-26B.; and a plurality of dielectric walls Fig 25A and 26A, 1002/1004/2402 extending lengthwise in the first direction, such that each of the plurality of dielectric walls extends in the first direction between multiple pairs of adjacent semiconductor devices Fig 16-17, Fig 20A-20B and Fig 25A-26B.
Regarding claim 22, You discloses wherein the plurality of dielectric walls comprises silicon and nitrogen, or silicon and oxygen ¶0031.
Regarding claim 23, You discloses wherein the plurality of dielectric walls extend in the first direction between adjacent source or drain regions of the multiple pairs of adjacent semiconductor devices Fig 16-17, Fig 20A-20B and Fig 25A-26B.
Regarding claim 25, You discloses spacer structures on sidewalls of each of the plurality of gate layers, wherein a dielectric material of the spacer structures is a same dielectric material as the plurality of dielectric walls¶0031 and 0035.
Regarding claim 26, You discloses wherein the plurality of dielectric walls have a substantially equal spacing in the second direction between adjacent dielectric walls Fig 16-17, Fig 20A-20B and Fig 25A-26B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, 18,19,20, 24 are rejected under 35 U.S.C. 103 as being unpatentable over You et al (US Publication No. 2022/0013410) in view of Hafez et al (US Publication No. 2019/0304971).
Regarding claims 4, 18 and 24, You discloses all the limitations but silent on the arrangement of the contacts. Whereas Hafez discloses a conductive layer Fig 8A-8B, 814/816 over a top surface of the dielectric wall Fig 8A-8B, 804/820, such that the conductive layer contacts the first gate layer on a first side of the dielectric wall and contacts the second gate layer on an opposite second side of the dielectric wall Fig 8A-8B. You and Hafez are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify You because they are from the same field of endeavor.
Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of the interconnect and incorporate the teachings of Hafez to improve device connectivity.
Regarding claims 7 and 20, You is silent on the PCB. Whereas Hafez discloses a printed circuit board comprising the integrated circuit of claim 1 Fig 10. You and Hafez are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify You because they are from the same field of endeavor.
Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of You and incorporate the teachings of Hafez to provide an improved integrated circuit.
Regarding claim 19, You in view of Hafez discloses a sidewall spacers along sidewalls of the first gate structure and the third gate structure Fig 16-17, Fig 20A-20B and Fig 25A-26B, wherein the conductive layer is aligned between the sidewall spacers Fig 16-17, Fig 20A-20B and Fig 25A-26B.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811