DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/12/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 16-18 and 20 are rejected under U.S.C. 103 as being unpatentable over Lu et al.; US 2021/0005708 A1; 03/2019 in view of Akahoshi et. al; US 2019/0215963 A1; 03/2019.
Claim 1: Lu discloses a chip part, comprising: a first electrode ( Fig. 1 #150 ), disposed on the capacitive film ( as shown in Fig. 1 ) ; a second electrode ( Fig. 1 #140 ), disposed on the second main surface (as shown in Fig. 1) ; a conductive layer ( [0175] the laminated structure #130 includes m insulating layers and n conductive layers ), disposed between the capacitive film ( Fig. 1 #170 ) and the semiconductor substrate ( Fig. 1 #110 ); and a plurality of penetrating conductive layers ( [0175] the laminated structure #130 includes m insulating layer(s) and n conductive layers ) penetrating the semiconductor substrate in a thickness direction ( as shown in Fig. 1 ), electrically connecting the conductive layer and the second electrode ( [0175] the second electrode layer #150 is electrically connected to all even-numbered conductive layer(s) in then conductive layers disposed in the first trench group #10 ), wherein, in a plan view, the semiconductor substrate ( Fig. 1 #110 ) includes a portion where the plurality of penetrating conductive layers are collectively formed ( as shown in Fig. 1 ), and wherein the plurality of penetrating conductive layers ( Fig. 1 #130 ) includes a conductive via ( Fig. 1: one first via structure 40 ) embedded in a through hole ( Fig. 1: first trench group 10 ) penetrating the semiconductor substrate ( Fig. 1 #110 ) in the thickness direction ( as shown in Fig. 1 ).
Lu does not appear to disclose a semiconductor substrate, having a flat first main surface and a second main surface opposite to the first main surface; a capacitive film, disposed on the flat first main surface; having a resistance lower than a resistance of the semiconductor substrate.
However, Akahoshi teaches a semiconductor substrate (Fig. 5C: base board 2), having a flat first main surface ( bottom of 2 as shown in Fig. 5C ) and a second main surface opposite to the first main surface ( top of 2 as shown in Fig. 5C ); a capacitive film ( Fig. 5C capacitor 10 ), disposed on the flat first main surface ( bottom of 2 as shown in Fig. 5C ); having a resistance ( [0030] Various conductor materials are used for the electrode layer. Copper (Cu), nickel (Ni), or the like may be used) lower than a resistance of the semiconductor substrate ( [0033] for the adhesive layer various organic or inorganic adhesive materials are used. An epoxy resin-based adhesive is used for #20a and #20b. [0034] As the insulating layer various insulating materials having higher elastic modulus than the adhesive layer are used. An insulating material containing glass or glass is used or a resin or resin such as polyimide resin is used ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Akahoshi with Lu to implement having a resistance lower than a resistance of the semiconductor substrate because it would enhance the electrical conductivity of the device.
Claim 16: Lu and Akahoshi disclose the chip part of Claim 1 (as discussed above).
Lu teaches the conductive layer ([0073] each of the n conductive layers) includes at least one of a metal layer ([0074] a metal layer) and a polycrystalline silicon (polysilicon) layer ([0074] a heavily doped polysilicon layer).
Claim 17: Lu discloses the chip part of Claim 1 (as discussed above),
Lu does not appear to disclose the semiconductor substrate has a thickness between 80 micrometers (µm) and 150 µm.
However, Akahoshi teaches the semiconductor substrate has a thickness between 80 micrometers (µm) and 150 µm ( [ 0077] the thickness of the insulating layer #30a is, for example, 50 µm to 100 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Akahoshi with Lu to implement the semiconductor substrate with a thickness between 80 micrometers (µm) and 150 µm because increasing substrate thickness can significantly increase capacitance.
Claim 18: Lu and Akahoshi disclose the chip part of Claim 1 ( as discussed above).
Lu teaches the semiconductor substrate includes a silicon substrate ( [0170] a silicon substrate).
Claim 20: Lu and Akahoshi disclose the chip part of Claim 1 (as discussed above).
Lu teaches the capacitive film includes at least one selected from a group including of SiO2 film, SiN film, ON film, ONO film, A1203 film and Ti3Os film ( [0196] each of the m insulating layers includes at least one of the following layers: a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal oxide layer, a metal nitride layer, and a metal oxynitride layer).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al.; US 2021/0005708 A1; 03/2019 in view of Akahoshi et. al; US 20190215963 A1; 03/2019 as applied to claim 3 above, and further in view of Yook et. al; US 2020/0137889 A1; 10/2019.
Claim 4: Lu and Akahoshi disclose the chip part of Claim 1 ( as discussed above).
Neither Lu nor Akahoshi appear to disclose the plurality of penetrating conductive layers are, in a plan view, arranged in a matrix over an entirety of the first main surface of the semiconductor substrate.
However, Yook teaches the plurality of penetrating conductive layers (#101) are, in a plan view, arranged in a matrix (Fig. 1 3 x 3 matrix of #101 shown) over an entirety of the first main surface (Fig. 2 #100a) of the semiconductor substrate (Fig. 2 #100).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Yook with Lu and Akahoshi to implement a plurality of penetrating conductive layers, in a plan view, arranged in a matrix over an entirety of the first main surface of the semiconductor substrate because it can be used for EMI shielding or specific sensing capabilities due to increased electrical conductivity.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al.; US 2021/0005708 A1; 03/2019 in view of Wang et al.; US 9412806 B2; 06/2014.
Claim 15: Lu discloses the chip part of Claim 1 ( as discussed above).
Lu does not appear to disclose the conductive layer covers an entirety of the first main surface of the semiconductor substrate.
However, Wang teaches the conductive layer ( Fig. 3C #110) covers an entirety of the first main surface ( as shown in Fig. 3C) of the semiconductor substrate ( Fig. 3C #100).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Wang with Lu to implement the conductive layer covers an entirety of the first main surface of the semiconductor substrate because this ensures a uniform and predictable electric field.
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Lu et al.; US 2021/0005708 A1; 03/2019 in view of Iio et. al; US 10,035,897 B2; 07/2018.
Claim 19: Lu discloses the chip part of Claim 1 (as discussed above),
Lu does not appear to disclose the capacitive film has a thickness between 2 µm and 8 µm
However, Iio teaches the capacitive film has a thickness between 2 µm and 8 µm ( Col 10 lines 11-14 it is desired that the thickness of the dielectric film more preferably 5 µm or more and 200 µm or less).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Iio with Lu to implement the capacitive film with a thickness between 2 µm and 8 µm because the application may be a capacitive touchscreen which requires precise and thin dielectric layers.
Response to Amendment / Arguments
Applicant’s arguments, see pages 6 - 8 of remarks, filed 05/12/2026, with respect to the rejection of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Akahoshi.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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