DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed August 5, 2025 has been entered. Applicant' s amendments to the Specification have overcome the objection set forth in the Non-Final Office Action mailed May 5, 2025, and the objection is hereby withdrawn.
Claims 1-14 and newly added claim 15 are pending in the application
Response to Arguments
Applicant’s arguments, see pages 7-9, filed August 5, 2025, with respect to the rejections of claims 1, 5, and 9-13 under 35 U.S.C 102(a)(1) and to the rejections of claims 2-4, 6-8 and 14 under 35 U.S.C 103 have been fully considered in view of the Amendment and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration in view of the Amendment, a new ground(s) of rejection is made in view of previously cited references. Please see the updated claim rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 5-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiura; Kuniaki (US 2017/0069683; hereinafter Sugiura) in view of Seong; Dong-Jun et al. (US 2021/0193736; hereinafter Seong).
Regarding claim 1, Sugiura discloses a magnetic memory device (see the included Fig 13 below; entire document) comprising:
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a magnetoresistance effect element portion (magnetic tunnel junction element (MTJ) 20, comprising 21-23; Fig 13; ¶ [0018, 0025, 0071]);
a switching element portion (MOS transistor; Figs 12-13; ¶ [0071-76]) provided on a lower layer side of the magnetoresistance effect element portion;
a buffer insulating portion (insulating underlayer 12; Fig 13; ¶ [0021-25, 0079]) provided between the magnetoresistance effect element portion and the switching element portion; and
a conductive portion (sidewall conducting film 32; Fig 13; ¶ [0029, 0032, 0079-81]) surrounding a side surface of the buffer insulating portion and electrically connecting the magnetoresistance effect element portion and the switching element portion to each other [0081; connected through lower electrode 115 (¶ [0077-79]) and buffer layer 11 (¶ [0021-22]).
Sugiura does not disclose the switching element portion being a 2- terminal switching element.
In the same field of endeavor, Seong discloses a magnetic memory device comprising a magnetoresistance effect element portion (variable resistance layer, MTJ 132; Fig 3 {see below}; ¶ [0039, 0050]) and a switching element portion (BE, 134, ME; Fig 3; ¶ [0039, 0054-63]), the switching element portion being a 2- terminal switching element (the two terminals being BE,ME).
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Accordingly, it would have obvious to a person having ordinary skill in the art that the three-terminal (MOS transistor) switching element portion of Sugiura may be replaced with a 2-terminal switching element portion similar that that disclosed by Seong. One would have been motivated to do this in order to reduce the size of the memory device of Sugiura, such as by reducing the width of the switching element for implementation in a cross-point structure such as that disclosed by Seong (Seong; Figs 2-3; ¶ [0003-4]), while maintaining Sugiura’s insulating underlayer 12 (buffer insulating portion) as crystallization acceleration layer (Sugiura; ¶ [0021, 0023]) and associated conductive portion (Sugiura; 32). One would have had a reasonable expectation of success because both types of switching elements are well known in the art and each has been shown in a magnetic memory device implementation with an MTJ magnetoresistance effect element by the disclosures of Sugiura and Seong respectively.
Regarding claim 5, Sugiura in view of Seong discloses the device of claim 1, wherein the buffer insulating portion (Sugiura; 12; Fig 13) contains silicon (Si) and oxygen (0), or silicon (Si) and nitrogen (N) (Sugiura; SiN; ¶ [0023]).
Regarding claim 6, Sugiura in view of Seong discloses the device of claim 1, wherein the switching element portion includes a bottom electrode (Seong; BE; Fig 3; ¶ [0039, 0061-63]), a top electrode (Seong; ME; Fig 3; ¶ [0039, 0061-63]), and a switching material layer (Seong; selection device 134; Fig 3; ¶ [0039, 0054-60]) provided between the bottom electrode and the top electrode.
Regarding claim 7, Sugiura in view of Seong discloses the device of claim 6, wherein the switching material layer (Seong; 134; Fig 3) is formed of an insulating material containing a metal element (¶ [0056-59]; the Examiner notes that the cited paragraphs include Te, As, S, Se, Sb as exemplary material elements, which are also listed as exemplary metal elements for the switching material layer in the instant application {p. 5, lines 4-10}).
Regarding claim 8, Sugiura in view of Seong discloses the device of claim 6, wherein the conductive portion (Sugiura; 32; Fig 13) is connected to the top electrode of the switching element portion (Seong; ME; Fig 3; as applied to claim 6, it would have been obvious in replacing the switching element portion of Sugiura with that of Seong that the conductive portion is connected to the top electrode of the switching element portion, the switching element portion being below the magnetoresistance effect element portion as disclosed by both Sugiura and Seong.)
Regarding claim 9, Sugiura in view of Seong discloses the device of claim 1, wherein the switching element portion (Seong; BE, 134, ME; Fig 3) changes from an off state to an on state when a voltage applied between terminals thereof becomes greater than or equal to a predetermined voltage (134 may be shifted between off state and on state, by applying a voltage, VT; ¶ [0084-87]).
Regarding claim 10, Sugiura in view of Seong discloses the device of claim 1, wherein the magnetoresistance effect element portion (Sugiura; 20, comprising 21-23; Fig 13) includes a first magnetic layer (Sugiura; 21; Fig 13; ¶ [0026]) having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction (Sugiura; 23; Fig 13; ¶ [0026]), and a nonmagnetic layer (Sugiura; 22; Fig 13; ¶ [0025-26]) provided between the first magnetic layer and the second magnetic layer.
Regarding claim 11, Sugiura in view of Seong discloses the device of claim 10, wherein the conductive portion (Sugiura; 32; Fig 13) is connected (as shown in Fig 13; ¶ [0030]) to a magnetic layer (Sugiura; 21; Fig 13) located on a lower layer side from among the first magnetic layer (Sugiura; 21; Fig 13) and the second magnetic layer (Sugiura; 23; Fig 13; layer 21 is on the lower side from among 21 and 23).
Regarding claim 12, Sugiura in view of Seong discloses the magnetic memory device of claim 1, further comprising: a sidewall insulating portion (Sugiura; 31; Fig 13; ¶ [0028]) provided along a sidewall of the magnetoresistance effect element portion (20; Fig 13).
Regarding claim 13, Sugiura in view of Seong discloses the magnetic memory device of claim 12, wherein the sidewall insulating portion (Sugiura; 31, comprising for example, silicon dioxide; Fig 13; ¶ [0028]) is formed of a material different from a material of the buffer insulating portion (Sugiura; 12, comprising, for example MgO; Fig 13; ¶ [0023]).
Regarding claim 14, Sugiura in view of Seong discloses the device of claim 1, but does not disclose further comprising: a first wiring line extending in a first direction; and a second wiring line extending in a second direction intersecting the first direction, wherein a structure including the magnetoresistance effect element portion, the switching element portion, and the buffer insulating portion is provided between the first wiring line and the second wiring line.
However, Seong discloses a first wiring line (110, extending in the X-direction; Figs 2-3; ¶ [0038]) extending in a first direction; and a second wiring line (120, extending in the Y-direction; Figs 2-3; ¶ [0038]) extending in a second direction intersecting the first direction, wherein a structure (130; Figs 2-3) including a magnetoresistance effect element portion (132; Fig 3), a switching element portion (134; Fig 3) and a connection therebetween (ME; Fig 3; ¶ [0061-63]) is provided between the first wiring line and the second wiring line.
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It would have been obvious, in implementing Sugiura in view of Seong in in a cross-point structure according to claim 1 to have included the first wiring line and the second wiring line of Seong, with the structure of claim 14 (maintaining Sugiura’s insulating underlayer 12 {buffer insulating portion}, as explained under claim 1). One would have been motivated to do this, with a reasonable expectation of success, because this type of cross-point structure is well-known in the art.
Claims 2-4, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiura; Kuniaki (US 2017/0069683; hereinafter Sugiura) in view of Seong; Dong-Jun et al. (US 2021/0193736; hereinafter Seong) and further in view of Ahn; Sung-Min et al. (US 2017/0148848; hereinafter Ahn).
Regarding claim 2, Sugiura in view of Seong discloses the device of claim 1, but does not disclose:
wherein a pattern of an upper surface of the buffer insulating portion is located inside a pattern of a lower surface of the magnetoresistance effect element portion as viewed from a direction in which the magnetoresistance effect element portion, the buffer insulating portion, and the switching element portion are arranged.
In the same field of endeavor, Ahn discloses a magnetic memory device (see the figures included below) comprising a magnetoresistance effect element portion (MTJ 55; Fig 1; ¶ [0081]) and including a metal oxide pattern 75 (Fig 1; ¶ [0081, 0091]), a conductive pattern 90 (Figs 1-3; ¶ [0081, 0092-97]) on a sidewall of the metal oxide pattern 75, and an upper electrode 85 (Fig 1; ¶ [0081, 0085]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art that a sidewall conductive pattern, having a structure such as 90 disclosed by Ahn, may be used to electrically connect MTJ elements of a memory device to another element of the memory device, and that the conductive portion (Sugiura; 32; Fig 13) and the buffer insulating portion (Sugiura; 12; Fig 13) may then take the form of 90 and 75 respectively disclosed by Ahn, the resulting structure of the semiconductor memory device of Sugiura in view of Seong, and further in view of Ahn then comprising a pattern of an upper surface of the buffer insulating portion (structured as 75 of Ahn) located inside a pattern of a lower surface of the magnetoresistance effect element portion (structured as 55 of Ahn) as viewed from a direction in which the magnetoresistance effect element portion, the buffer insulating portion, and the switching element portion are arranged (55/75/85, as shown in Ahn Figs 1-3, for the analogous structure; along the vertical direction of Fig 3 of Ahn).
One would have been motivated to do this as an equivalent alternate structure versus that disclosed by Sugiura (Sugiura having the conductive portion 32 exterior to the sidewalls of those elements it connects), which may have, for example, a preferable formation sequence in the manufacturing process. One would have had a reasonable expectation of success due to the similar elements and endeavors.
Regarding claim 3, Sugiura in view of Seong discloses the device of claim 1, but does not disclose:
wherein an outer circumference of an upper surface of the conductive portion is aligned with an outer circumference of a lower surface of the magnetoresistance effect element portion as viewed from a direction in which the magnetoresistance effect element portion, the buffer insulating portion, and the switching element portion are arranged.
In the same field of endeavor, Ahn discloses a semiconductor memory device (see the figures included below) comprising a magnetoresistance effect element portion (MTJ 55; Fig 1; ¶ [0081]) and including a metal oxide pattern 75 (Fig 1; ¶ [0081, 0091]), a conductive pattern 90 (Figs 1-3; ¶ [0081, 0092-97]) on a sidewall of the metal oxide pattern 75, and an upper electrode 85 (Fig 1; ¶ [0081, 0085]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art that a sidewall conductive pattern, having a structure such as 90 disclosed by Ahn, may be used to electrically connect MTJ elements of a memory device to another element of the memory device, and that the conductive portion (Sugiura; 32; Fig 13) and the buffer insulating portion (Sugiura; 12; Fig 13) may then take the form of 90 and 75 respectively disclosed by Ahn, the resulting structure of the semiconductor memory device of Sugiura in view of Seong and further in view of Ahn then comprising an outer circumference of an upper surface of the conductive portion (structured as 90 of Ahn) is aligned with an outer circumference of a lower surface of the magnetoresistance effect element portion as viewed from a direction in which the magnetoresistance effect element portion (structured as 55 of Ahn), the buffer insulating portion, and the switching element portion are arranged (55/75/85, as shown in Ahn Figs 1-3, for the analogous structure; along the vertical direction of Fig 3 of Ahn).
One would have been motivated to do this as an equivalent alternate structure versus that disclosed by Sugiura (Sugiura having the conductive portion 32 exterior to the sidewalls of those elements it connects), which may have, for example, a preferable formation sequence in the manufacturing process. One would have had a reasonable expectation of success due to the similar elements and endeavors.
Regarding claim 4, Sugiura in view of Seong discloses the device of claim 1, but does not disclose:
wherein an outer circumference of a lower surface of the conductive portion is aligned with an outer circumference of an upper surface of the switching element portion as viewed from a direction in which the magnetoresistance effect element portion, the buffer insulating portion, and the switching element portion are arranged.
In the same field of endeavor, Ahn discloses a semiconductor memory device (see the figures included below) comprising a magnetoresistance effect element portion (MTJ 55; Fig 1; ¶ [0081]) and including a metal oxide pattern 75 (Fig 1; ¶ [0081, 0091]), a conductive pattern 90 (Figs 1-3; ¶ [0081, 0092-97]) on a sidewall of the metal oxide pattern 75, and an upper electrode 85 (Fig 1; ¶ [0081, 0085]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art that a sidewall conductive pattern, have a structure such as 90 disclosed by Ahn, may be used to electrically connect MTJ elements of a memory device to another element of the memory device, and that the conductive portion (Sugiura; 32; Fig 13) and the buffer insulating portion (Sugiura; 12; Fig 13) may then take the form of 90 and 75 respectively disclosed by Ahn, the resulting structure of the semiconductor memory device of Sugiura in view of Seong and further in view of Ahn then comprising an outer circumference of a lower surface of the conductive portion (structured as 90 of Ahn) is aligned with an outer circumference of an upper surface of the switching element portion (structured as 85 of Ahn) as viewed from a direction in which the magnetoresistance effect element portion, the buffer insulating portion, and the switching element portion are arranged (55/75/85, as shown in Ahn Figs 1-3, for the analogous structure; along the vertical direction of Fig 3 of Ahn, for the analogous structure wherein the switching element portion takes the location of Ahn 85).
One would have been motivated to do this as an equivalent alternate structure versus that disclosed by Sugiura (Sugiura having the conductive portion 32 exterior to the sidewalls of those elements it connects), which may have, for example, a preferable formation sequence in the manufacturing process. One would have had a reasonable expectation of success due to the similar elements and endeavors.
Regarding claim 15, Sugiura in view of Seong discloses the device of claim 1, but does not disclose wherein an upper end of the conductive portion is not located higher than a bottom surface of the magnetoresistance effect element portion.
In the same field of endeavor, Ahn discloses a semiconductor memory device (see the figures included below) comprising a magnetoresistance effect element portion (MTJ 55; Fig 1; ¶ [0081]) and including a metal oxide pattern 75 (Fig 1; ¶ [0081, 0091]), a conductive pattern 90 (Figs 1-3; ¶ [0081, 0092-97]) on a sidewall of the metal oxide pattern 75, and an upper electrode 85 (Fig 1; ¶ [0081, 0085]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art that a sidewall conductive pattern, have a structure such as 90 disclosed by Ahn, may be used to electrically connect MTJ elements of a memory device to another element of the memory device, and that the conductive portion (Sugiura; 32; Fig 13) and the buffer insulating portion (Sugiura; 12; Fig 13) may then take the form of 90 and 75 respectively disclosed by Ahn, the resulting structure of the semiconductor memory device of Sugiura in view of Seong and further in view of Ahn then comprising an upper end of the conductive portion (structured as 90 {Fig 3} surrounding 75 {Fig 3} of Ahn in place of Sugiura 32 {Fig 13} surrounding Sugiura 12 {Fig 13}) is not located higher than a bottom surface of the magnetoresistance effect element portion (Sugiura; 20, comprising 21-23; Fig 13).
One would have been motivated to do this as an equivalent alternate structure versus that disclosed by Sugiura (Sugiura having the conductive portion 32 exterior to the sidewalls of those elements it connects), which may have, for example, a preferable formation sequence in the manufacturing process. One would have had a reasonable expectation of success due to the similar elements and endeavors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Doyle; Brian S. et al. (US 2016/0351238; the prior art discloses a memory element comprising an annular conductive spacer surrounding a sidewall of an insulative layer, and contained between two conductive layers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817