DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (encompassing claims 1-11) in the reply filed on 11/5/25 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 9/13/22 and 11/20/25. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s):
In at least Fig. 1A, the trench isolation region as distinct from isolation region (claims 1, 8);
The plurality of first fin structures in the dense array region further comprise a gate structure and source and drain regions (from at least claim 3) (Examiner notes Fig. 1B does not sufficiently illustrate this feature because in Fig. 1A, the fin structures comprise nanosheets 6 and 7. In Fig. 1B, there are no parts that correspond to nanosheets 6 and 7. Therefore, it is unclear how the gate structure 51 and source drain regions 50 of Fig. 1B would be incorporated into the broader device of Fig. 1A);
The at least one second fin structure comprises a gate structure and source and drain regions (from at least claim 4) (Examiner notes Fig. 1B does not sufficiently illustrate this feature because in Fig. 1A, the fin structures comprise nanosheets 6 and 7. In Fig. 1B, there are no parts that correspond to nanosheets 6 and 7. Therefore, it is unclear how the gate structure 51 and source drain regions 50 would be incorporated into the broader device of Fig. 1A);
A plurality of first field effect transistors having channel regions present in a first plurality of first fin structures of stacked nanosheets is present in the dense array region and at least one second field effect transistor having channel regions present in at least one second fin structure comprised of stacked nanosheets is present in the isolation region (from at least claim 8) (Examiner notes that neither Fig. 1A nor Fig. 9 illustrate transistors (i.e., structures containing at least a source, drain, and gate) in the dense array and/or isolation array in the dense array and/or isolation array. Fig. 1B seemingly illustrates a source and drain region and gate structure but it is unclear how the structure of Fig. 1B is incorporated into the broader device of Fig. 1A or Fig. 9 because the latter figures contain nanosheets 6 and 7 whereas Fig. 1B does not contain parts that correspond to nanosheets 6 and 7);
The stacked nanosheets in the plurality of first fin structures includes a first nanosheet having a first silicon and germanium composition, and a second nanosheet having a second silicon and germanium composition, wherein a germanium content of the first silicon and germanium composition is different from a germanium content of the second silicon and germanium composition (from at least claim 10) (Examiner notes that neither Fig. 1A nor Fig. 9 illustrate transistors (i.e., structures containing at least a source, drain, and gate) in the dense array and/or isolation array. Fig. 1B seemingly illustrates a source and drain region and gate structure but it is unclear how the structure of Fig. 1B is incorporated into the broader device of Fig. 1A or Fig. 9 because the latter figures contain nanosheets 6 and 7 whereas Fig. 1B does not contain parts that correspond to nanosheets 6 and 7).
No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 3 objected to because of the following informalities:
In claim 3, line 3 change “structure” to - - structures - -;
In claim 5, line 3, change “a germanium” to - - and germanium - -;
In claim 10, line 3 change “an germanium” to - - and germanium - -.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 8 state “the dense array region and the isolation region are separated by a trench isolation region” (lines 2-3). As written, this implies the trench isolation region is distinct from the dense array region and the isolation region since it is differentiated or labelled differently from the dense array region and the isolation region. However, according to Fig. 1A, the trench isolation region (41, Fig. 1A) appears to be within the isolation region (20, Fig. 1A). Therefore, there is a conflict between the phrase “the dense array region and the isolation region are separated by a trench isolation region”, as written in the claim, and the way those regions are described in the Specification and Drawings. As such, it is unclear to the examiner if Applicant intended the trench isolation region, as referenced in at least claims 1 and 8, as part of the isolation region or distinct from the isolation region. For the purposes of examination, the examiner interprets claims 1 and 8 as-written (i.e., the trench isolation regions are not part of the isolation region). However, appropriate correction and/or clarification is requested.
Claims 2-7 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1. Claims 9-11 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 8.
Claim 10 states the stacked nanosheets include a first nanosheet and a second nanosheet have differing compositions. Claim 10 depends on claim 8. Claim 8 specifies a plurality of first field effect transistors having channel regions present in a first plurality of first fin structures of stacked nanosheets and at least one second field effect transistor having channel regions present in at least one second fin structure comprised of stacked nanosheets. However, it is unclear how the subject matter of claim 10 (first stacked nanosheet and second stacked nanosheet with differing compositions) is incorporated into parent claim 8 because the only embodiment in the Specification detailing a transistor (device comprising a source, drain, and gate) is in Fig. 1B and Fig. 1B does not illustrate first stacked nanosheets or second stacked nanosheets. Said another way, the neither the drawings nor the Specification illustrate or describe an embodiment that simultaneously contains a plurality of first field effect transistors having channel regions present in a first plurality of first fin structures of stacked nanosheets and at least one second field effect transistor having channel regions present in at least one second fin structure comprised of stacked nanosheets, wherein the stacked nanosheets include a first nanosheet and a second nanosheet, wherein the first nanosheet and the second nanosheet have differing compositions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 5-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (U.S. 2021/0375858 A1; “Chiang”).
Regarding claim 1, Chiang discloses a semiconductor device comprising:
A substrate (202, 202’, Fig. 5) having a dense array region (portion of substrate containing 222B - 222C, Fig. 5; see also Examiner Annotated Fig. 5 below) and an isolation region (portion of substrate containing 222A, Fig. 5; see also Examiner Annotated Fig. 5 below) ([0015]), wherein the dense array region and the isolation region are separated by a trench isolation region (235, Fig. 5) ([0020]);
A plurality of first fin structures (222B, 222C, Fig. 5) comprised of stacked nanosheets is present in the dense array region separated by a single pitch, wherein each fin structure in the first plurality of fin structures has a same first fin height as measured from an upper surface of the substrate in the dense array region ([0016], [0018]); and
At least one second fin structure (222A, Fig. 5) comprised of stacked nanosheets is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one second fin structure having a second fin height that is measured from the upper surface of the substrate in the isolation region that is the same as the first fin height ([0016], [0018]).
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Regarding claim 2, Chiang discloses the upper surface of the substrate (202, 202’, Fig. 5) in the dense array region (portion of substrate containing 222B - 222C, Fig. 5) is coplanar with the upper surface in the isolation region (portion of substrate containing 222A, Fig. 5).
Regarding claim 5, Chiang discloses the stacked nanosheets in the plurality of first fin structures includes a first nanosheet (215, Fig. 5) having a first silicon and germanium composition, and a second nanosheet (220, Fig. 5) having a second silicon a germanium composition, wherein a germanium content of the first silicon and germanium composition is different from a germanium content of the second silicon and germanium composition ([0016]).
Regarding claim 6, Chiang discloses the substrate (202, 202’, Fig. 5) is composed of silicon ([0015]).
Regarding claim 7, Chiang discloses the trench isolation region (235, Fig. 5) is filled with a solid dielectric ([0020]).
Claim(s) 1, 3-4, 8-9, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh et al. (U.S. 2017/0365604 A1; “Suh 1”).
Regarding claim 1, Suh 1 discloses a semiconductor device comprising:
A substrate (102, Fig. 23) having a dense array region (See Examiner Annotated Fig. 23 below) and an isolation region (See Examiner Annotated Fig. 23 below), wherein the dense array region and the isolation region are separated by a trench isolation region (114, Fig. 23) ([0024]);
A plurality of first fin structures comprised of stacked nanosheets (NSS, Fig. 23) is present in the dense array region separated by a single pitch, wherein each fin structure in the first plurality of fin structures has a same first fin height as measured from an upper surface of the substrate in the dense array region (See Examiner Annotated Fig. 23; [0038]); and
At least one second fin structure comprised of stacked nanosheets (NSS, Fig. 23) is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one second fin structure having a second fin height that is measured from the upper surface of the substrate in the isolation region that is the same as the first fin height (See Examiner Annotated Fig. 23; [0038]).
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Regarding claim 3, Suh 1 discloses the plurality of first fin structure in the dense array region further comprise a gate structure (150, Fig. 23) and source and drain regions (162A, Fig. 23) ([0078], [0060]-[0061]).
Regarding claim 4, Suh 1 discloses the at least one second fin structure comprises a gate structure (150, Fig. 23) and source and drain regions (164A, Fig. 23) ([0078], [0062]).
Regarding claim 8, Suh 1 discloses an electrical device comprising:
A substrate having a dense array region (see Examiner Annotated 2 Fig. 23 below) and an isolation region (see Examiner Annotated 2 Fig. 23 below), wherein the dense array region and the isolation region are separated by a trench isolation region (114, Fig. 23);
A plurality of first field effect transistors having channel regions present in a first plurality of first fin structures of stacked nanosheets (NSS, Fig. 23) is present in the dense array region separated by a single pitch, wherein each first fin structure has a same first fin height as measured from an upper surface of the substrate in the dense array region (see Examiner Annotated 2 Fig. 23 below; [0038]); and
At least one second field effect transistor having channel regions present in at least one second fin structure comprised of stacked nanosheets (NSS, Fig. 23) is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one second fin structure having a second fin height that is measured from the upper surface of the substrate in the isolation region that is the same as the first fin height (see Examiner Annotated 2 Fig. 23 below; [0038]).
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Regarding claim 9, Suh 1 discloses the upper surface of the substrate (102, Fig. 23) in the dense array region is coplanar with the upper surface in the isolation region (see Examiner Annotated 2 Fig. 23).
Regarding claim 11, Suh 1 discloses the substrate (102, Fig. 23) is composed of silicon ([0016]).
Claim(s) 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh et al. (U.S. 2017/0365604 A1; “Suh 2”).
Regarding claim 8, Suh 2 discloses an electrical device comprising:
A substrate having a dense array region (see Examiner Annotated Fig. 19 below) and an isolation region (see Examiner Annotated Fig. 19 below), wherein the dense array region and the isolation region are separated by a trench isolation region (114, Fig. 19);
A plurality of first field effect transistors having channel regions present in a first plurality of first fin structures of stacked nanosheets (NSS, Fig. 19) is present in the dense array region separated by a single pitch, wherein each first fin structure has a same first fin height as measured from an upper surface of the substrate in the dense array region (see Examiner Annotated Fig. 19 below; [0038]); and
At least one second field effect transistor having channel regions present in at least one second fin structure comprised of stacked nanosheets (NSS, Fig. 19) is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one second fin structure having a second fin height that is measured from the upper surface of the substrate in the isolation region that is the same as the first fin height (see Examiner Annotated Fig. 19; [0038]).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suh et al. (U.S. 2017/0365604 A1; “Suh 2”) as applied to claim 8 above, and further in view of Chiang et al. (U.S. 2021/0375858 A1; “Chiang”).
Regarding claim 10, Suh 2 discloses the stacked nanosheets include a first nanosheet having a first silicon and germanium composition and a second nanosheet ([0017]-[0018]) but do not disclose the second nanosheet has a second silicon and germanium composition different from that of the first nanosheet. However, Chiang discloses stacked nanosheets including a first nanosheet (215, Fig. 5) having a first silicon and germanium composition, and a second nanosheet (220, Fig. 5) having a second silicon a germanium composition, wherein a germanium content of the first silicon and germanium composition is different from a germanium content of the second silicon and germanium composition ([0016]). Because both Suh 2 and Chiang teach methods of forming stacked nanosheets including first nanosheets and second nanosheets with differing compositions, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of forming the second nanosheet having a second silicon a germanium composition, wherein a germanium content of the first silicon and germanium composition is different from a germanium content of the second silicon and germanium composition. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 11/24/2025