Prosecution Insights
Last updated: April 19, 2026
Application No. 17/943,812

DIODES WITH BACKSIDE CONTACT

Non-Final OA §102
Filed
Sep 13, 2022
Examiner
AHMED, SHAHED
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
91%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
866 granted / 955 resolved
+22.7% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
45 currently pending
Career history
1000
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 955 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to application No. 17943812 filed on 09/13/2022. Election/Restrictions Applicant’s election with traverse of claims 1-7, 12-22 in the reply filed on 12/17/2025 is acknowledged. Applicant argues that there is no serious search burden. The traversal is unpersuasive since the species require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species. The restriction requirement is maintained. Allowable subject matter Claims 2-7, 17-18 are objected (claim 18 pending resolution of claim objection) to as being dependent upon a rejected base claim (independent claims 1 & 16), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Huang et al. (US 2022/0045052). With respect to dependent claims 2-7, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the portion of the sub-fin is a first portion, and wherein the sub-fin further has a second portion between the diffusion region and the first portion of the sub-fin, the second portion doped differently from the first portion”. With respect to dependent claims 17-18, the cited prior art does not anticipate or make obvious, inter alia, the step of: “ the sub-fin comprises (i) a first portion that is doped with a first type of dopant, and (ii) a second portion that is doped with a second type of dopant, wherein the first type of dopant is one of a p-type or an n-type dopant, and wherein the second type of dopant is the other of the p-type or the n-type dopant; the diffusion region doped with the second type of dopant; and the first portion and the second portion in contact with each other, to form a PN junction of the diode structure therebetween”. Claim Objections Claim 18 depends on claim 16 and recites the limitation “the sub-fin further comprises a third portion…”. Claim 16 does not disclose the first and second portion, rather claim 17 discloses the first and second portion. Accordingly, it appears that claim 18 should depend on claim 17 and not claim 16. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 12-16, 19-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2022/0045052). Regarding independent claim 1, Huang et al. teach an integrated circuit structure comprising: a sub-fin (Fig. 1, element 102N, paragraph 0003, 0029 disclose a FinFET device, accordingly, element 102N is construed to be a sub-fin) having at least a portion that is doped with a first type of dopant (paragraph 0029 discloses n type dopant); a diffusion region (Fig. 1, element 116P, paragraph 0026 discloses p type dopant) doped with a second type of dopant, the diffusion region in contact with the sub-fin and extending upward from the sub-fin (Fig. 1), wherein the first type of dopant is one of a p-type or an n-type dopant (Fig, 1, paragraph 0029 discloses n type dopant), and wherein the second type of dopant is the other of the p-type (paragraph 0026 discloses p type dopant) or the n-type dopant; a first conductive contact (Fig. 1, element 120, paragraph 0026) above and on the diffusion region; and a second conductive contact (Fig. 1, element 130, paragraph 0029) in contact with the portion of the sub-fin. Regarding claim 12, Huang et al. teach wherein: the diffusion region is a first diffusion region (Fig. 1, left element 116P, paragraph 0026); the integrated circuit structure further comprises (i) a second diffusion region (Fig. 1, right element 116P, paragraph 0026) doped with the second type of dopant, the second diffusion region in contact with the sub-fin and extending upward from the sub-fin, (ii) one or more bodies (Fig. 1, elements 108, paragraph 0026) of semiconductor material extending from the first diffusion region to the second diffusion region, and (iii) a gate structure comprising a gate electrode electrode (Fig. 1, element 114, paragraph 0026) and gate dielectric (Fig. 1, elements 112, paragraph 0026) on the one or more bodies. Regarding claim 13, Huang et al. teach wherein the one or more bodies comprise one or more nanoribbons, one or more nanosheets, one or more nanowires (paragraph 0026), or a fin. Regarding claim 14, Huang et al. teach wherein the first conductive contact is one of an anode contact (Figs. 1 & 3, anode contact, paragraph 0033) or a cathode contact of a diode, and the second conductive contact is the other of the anode contact or the cathode contact (Figs. 1 & 3, cathode contact, paragraph 0033) of the diode. Regarding claim 15, Huang et al. teach wherein the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode (Figs. 1 & 3, paragraph 0033). Regarding independent claim 16, Huang et al. teach a diode structure (Figs. 1 & 3, elements 302 & 304, paragraph 0033) comprising: a sub-fin (Fig. 1, element 102N, paragraph 0003, 0029 disclose a FinFET device, accordingly, element 102N is construed to be a sub-fin); a first conductive contact (Fig. 1, element 130, paragraph 0029) in contact with the sub-fin, wherein the first conductive contact is one of an anode contact or a cathode contact (Figs. 1 & 3, cathode contact, paragraph 0033) of the diode structure; a diffusion region (Fig. 1, element 116P, paragraph 0026 discloses p type dopant) in contact with the sub-fin; and a second conductive contact (Fig. 1, element 120, paragraph 0026) in contact with the diffusion region, wherein the second conductive contact is the other of the anode contact (Figs. 1 & 3, anode contact, paragraph 0033) or the cathode contact of the diode structure. Regarding independent claim 19, Huang et al. teach an integrated circuit structure comprising: a sub-fin (Fig. 1, element 102N, paragraph 0003, 0029 disclose a FinFET device, accordingly, element 102N is construed to be a sub-fin); a first diffusion region (Fig. 1, left element 116P, paragraph 0026) and a second diffusion region (Fig. 1, right element 116P, paragraph 0026), each in contact with, and extending upward from, the sub-fin; one or more bodies (Fig. 1, elements 108, paragraph 0026) of semiconductor material extending laterally from the first diffusion region to the second diffusion region; a gate structure comprising a gate electrode (Fig. 1, element 114, paragraph 0026) and gate dielectric (Fig. 1, elements 112, paragraph 0026) on the one or more bodies; and a first conductive contact (Fig. 1, left element 120, paragraph 0026) comprising metal in contact with the first diffusion region, a second conductive contact (Fig. 1, right element 120, paragraph 0026) comprising metal in contact with the second diffusion region, and a third conductive contact (Fig. 1, element 130, paragraph 0029) comprising metal in contact with the sub-fin. Regarding claim 20, Huang et al. teach wherein the one or more bodies of semiconductor material comprise one or more nanoribbons, one or more nanosheets, one or more nanowires (paragraph 0026), or a fin. Regarding claim 21, Huang et al. teach wherein the first and second conductive contacts collectively form one of an anode contact (Figs. 1 & 3, anode contact) or a cathode contact of a diode, and the third conductive contact forms the other of the anode contact or the cathode contact (Figs. 1 & 3, cathode contact, paragraph 0033) of the diode. Regarding claim 22, Huang et al. teach wherein the first conductive contact and the second conductive contact are coupled to a same terminal (Fig. 1, element 202, paragraph 0033). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHED AHMED/ Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Sep 13, 2022
Application Filed
Apr 12, 2023
Response after Non-Final Action
Mar 03, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
91%
With Interview (+0.0%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 955 resolved cases by this examiner. Grant probability derived from career allow rate.

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