DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A in the reply filed on December 29, 2025 is acknowledged.
Applicant's election with traverse of Species A in the reply filed on December 29, 2025 is acknowledged. The traversal is on the ground(s) that there is no excessive burden to examine both species. This is not found persuasive because Examiner has noted that the species required a different field of search due to their mutually exclusive characteristics.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claims 1-5, 8-10, and 22 are objected to because of the following informalities:
Applicant switches between “first/second body of semiconductor material” and “first/second body” in the claims to refer to the same component. Applicant is asked to choose one naming convention for the component.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, the claim recites the limitation “the third sub-fin” in lines 5-6. There is insufficient antecedent basis for this limitation in the claim. It is not clear where the third-sub-fin is located. For purposes of examination, Examiner will interpret this to mean “the third portion of the sub-fin.”
Further, the claim recites the limitation “the third first portion of the sub-fin” in line 7. There is insufficient antecedent basis for this limitation in the claim. It is not clear if the third portion of the sub-fin or the first portion of the sub-fin is meant. For purposes of examination, Examiner will interpret this to mean “the third portion of the sub-fin”
Regarding claim 22, the claim recites the limitation “the first sub-fin” in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner will interpret this to mean “the first portion of the sub-fin.”
Further, the claim recites the limitation “the second sub-fin” in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner will interpret this to mean “the second portion of the sub-fin.”
Additionally, the claim recites the limitation “the third sub-fin” in line 6. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner will interpret this to mean “the third portion of the sub-fin.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-10, and 15-22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liaw (US 20240387674 A1).
Regarding claim 1, Liaw teaches an integrated circuit structure (Fig 10 GAA device 200, [0023]), comprising: a sub-fin (Fig 12 regions 204A/B, [0026]) having (i) a first portion (Fig 12 region 204A, [0027]) comprising a p-type dopant (p-type, [0201]) and (ii) a second portion (Fig 12 region 204B, [0027]) comprising an n-type dopant (n-type, [0027]); a first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) of semiconductor material (semiconductor, [0030]) above the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); and a second body (Fig 12 semiconductor layer 215 over region 204B, [0030]) of semiconductor material (semiconductor, [0030]) above the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); wherein the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) are in contact with each other (Fig 12), to form a PN junction (Fig 12).
Regarding claim 8, Liaw teaches the sub-fin (Fig 12 regions 204A/B, [0026]) and the first (Fig 12 semiconductor layer 215 over region 204A, [0030]) and second bodies (Fig 12 semiconductor layer 215 over region 204B, [0030]) are part of a diode structure (See annotated figure; Fig 1 was chosen because it also shows first and second portions), wherein the integrated circuit structure (Fig 10 GAA device 200, [0023]) further comprises: a transistor structure (See annotated figure; Fig 1 was chosen because it also shows first and second portions) laterally adjacent to the diode structure, wherein the transistor structure (See annotated figure; Fig 1 was chosen because it also shows first and second portions) includes (i) a first source or drain region (Fig 11 left source/drain feature 260B, [0030]), (ii) a second source or drain region (Fig 11 right source/drain feature 260B, [0030]), and (iii) a third body (Fig 11 semiconductor layer 215 between source/drain feature 260B, [0030]) of semiconductor material (semiconductor, [0030]) extending from the first source or drain region (Fig 11 left source/drain feature 260B, [0030]) to the second source or drain region (Fig 11 right source/drain feature 260B, [0030]), wherein the first (Fig 12 semiconductor layer 215 over region 204A, [0030]), second (Fig 12 semiconductor layer 215 over region 204B, [0030]), and third bodies (Fig 11 semiconductor layer 215 between source/drain feature 260B, [0030]) extend in a first direction (Fig 10 up/down), wherein the first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) has a first width (Fig 3 width W1, [0032]) extending in a second direction (Fig 10 left/right) orthogonal to the first direction (Fig 10 up/down), and the third body (Fig 11 semiconductor layer 215 between source/drain feature 260B, [0030]) has a second width (Fig 3 width W2, [0032]) extending in the second direction (Fig 10 left/right), and wherein the first width (Fig 3 width W1, [0032]) is at least 10% more than (ratio of widths W1 and W2 may be in a range of 1.05 to 2, [0032]; Examiner notes that Liaw teaches W1 can be greater than W2 or vice versa; Examiner notes the ratio of 1.05-2 can mean a percentage increase of 5%-100%) the second width (Fig 3 width W2, [0032]).
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Regarding claim 9, Liaw teaches the sub-fin (Fig 12 regions 204A/B, [0026]) and the first (Fig 12 semiconductor layer 215 over region 204A, [0030]) and second bodies (Fig 12 semiconductor layer 215 over region 204B, [0030]) are part of a diode structure (See annotated figure of Fig 8; Fig 1 was chosen because it also shows first and second portions), wherein the integrated circuit structure (Fig 10 GAA device 200, [0023]) further comprises: a transistor structure (See annotated figure of Fig 8; Fig 1 was chosen because it also shows first and second portions) laterally adjacent to the diode structure, wherein the transistor structure (See annotated figure; Fig 1 was chosen because it also shows first and second portions) includes (i) a first source or drain region (Fig 11 left source/drain feature 260B, [0030]), (ii) a second source or drain region (Fig 11 right source/drain feature 260B, [0030]), and (iii) a third body (Fig 11 semiconductor layer 215 between source/drain feature 260B, [0030]) of semiconductor material (semiconductor, [0030]) extending from the first source or drain region (Fig 11 left source/drain feature 260B, [0030]) to the second source or drain region (Fig 11 right source/drain feature 260B, [0030]), wherein the first (Fig 12 semiconductor layer 215 over region 204A, [0030]), second (Fig 12 semiconductor layer 215 over region 204B, [0030]), and third bodies (Fig 11 semiconductor layer 215 between source/drain feature 260B, [0030]) extend in a first direction (Fig 10 up/down), wherein the first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) has a first width (Fig 3 width W1, [0032]) extending in a second direction (Fig 10 left/right) orthogonal to the first direction (Fig 10 up/down), and the third body (Fig 11 semiconductor layer 215 between source/drain feature 260B, [0030]) has a second width (Fig 3 width W2, [0032]) extending in the second direction (Fig 10 left/right), and wherein the first width (Fig 3 width W1, [0032]) is at least 2 nanometers more (widths W1 and W2 may be in a range of 4nm to 10nm; Examiner notes that Liaw teaches W1 can be greater than W2 or vice versa; Examiner notes choosing a width of 4nm and a ratio of 1.5 or higher will result in one width being 2nm or more than the other width) than the second width (Fig 3 width W2, [0032]).
Regarding claim 10, Liaw teaches a first diffusion region (Fig 13 source/drain feature 260A, [0030]) in contact with the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); a second diffusion region (Fig 13 source/drain feature 260B, [0030]) in contact with the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]), wherein the first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) extends from the first diffusion region (Fig 13 source/drain feature 260A, [0030]) towards (See annotated figure of claim 2; Fig 1 was chosen because it also shows first and second portions) the second diffusion region (Fig 13 source/drain feature 260B, [0030]), and wherein the second body (Fig 12 semiconductor layer 215 over region 204B, [0030]) extends from the second diffusion region (Fig 13 source/drain feature 260B, [0030]) towards (See annotated figure of claim 2; Fig 1 was chosen because it also shows first and second portions) the first diffusion region (Fig 13 source/drain feature 260A, [0030]); wherein the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and the first diffusion region (Fig 13 source/drain feature 260A, [0030]) are an anode of a diode structure, and wherein the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and the second diffusion region (Fig 13 source/drain feature 260B, [0030]) are a cathode of the diode structure.
Examiner notes that the structure of Liaw is substantially identical to that of the limitation in lines 7-9. Thus, the portions would be able to perform the same function of the limitation. MPEP 2112.01
Regarding claim 15, Liaw teaches the PN junction (Fig 12) between the first (Fig 12 region 204A, [0027]) and second portions(Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) is a first PN junction (Fig 10 left PN junction between the p and n wells), and wherein the integrated circuit structure (Fig 10 GAA device 200, [0023]) further comprises: a third portion (Fig 10 right p well) of the sub-fin (Fig 12 regions 204A/B, [0026]) comprising p-type dopant (p-type, [0201]), wherein the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) is laterally between (One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the n well and p well locations can be rearranged with subsequent processing changed in accordance with the well type with no change in the operation of transistors once; changing the locations of the well would result in the second portion being between the first and third portions MPEP 2144.04(VI)(C)) the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and the third portion (Fig 12 region 204A, [0027]) of the third sub- fin (Fig 12 regions 204A/B, [0026]); and a third body (Fig 12 semiconductor layer 215 over region 204A, [0030]) of semiconductor material (semiconductor, [0030]) above the third first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); wherein the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and the third portion of the sub-fin (Fig 12 regions 204A/B, [0026]) are in contact with each other (Fig 12), to form a second PN junction (once modified as noted above there will be a second PN junction where the wells meet).
Regarding claim 16, Liaw teaches an integrated circuit structure (Fig 10 GAA device 200, [0023]), comprising: a sub-fin (Fig 12 regions 204A/B, [0026]) having a first portion (Fig 12 region 204A, [0027]) comprising a p-type dopant (p-type, [0201]) and a second portion (Fig 12 region 204B, [0027]) comprising an n- type dopant (n-type, [0027]); a first diffusion region (Fig 13 source/drain feature 260A, [0030]) in contact with the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]), the first diffusion region (Fig 13 source/drain feature 260A, [0030]) comprising p-type dopant (p-type, [0201]); and a second diffusion region (Fig 13 source/drain feature 260B, [0030]) in contact with the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]), the second diffusion region (Fig 13 source/drain feature 260B, [0030]) comprising n-type dopant (n-type, [0027]); wherein the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) are in contact with each other (Fig 12), to form a PN junction (Fig 12).
Regarding claim 17, Liaw teaches a first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) of semiconductor material (semiconductor, [0030]) above the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and extending from the first diffusion region (Fig 13 source/drain feature 260A, [0030]) toward the (See annotated figure; Fig 1 was chosen because it also shows first and second portions) second diffusion region (Fig 13 source/drain feature 260B, [0030]); a second body (Fig 12 semiconductor layer 215 over region 204B, [0030]) of semiconductor material (semiconductor, [0030]) above the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) and extending from the second diffusion region (Fig 13 source/drain feature 260B, [0030]) toward the (See annotated figure; Fig 1 was chosen because it also shows first and second portions) first diffusion region (Fig 13 source/drain feature 260A, [0030]); and a dielectric structure (Fig 12 dielectric lines 414, [0047]) between and separating the first (Fig 12 semiconductor layer 215 over region 204A, [0030]) and second bodies (Fig 12 semiconductor layer 215 over region 204B, [0030]).
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Regarding claim 18, Liaw teaches a first gate structure (Fig 12 gate electrode layer 350 over region 204A, [0033]) on the first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) of semiconductor material (semiconductor, [0030]); and a second gate structure (Fig 12 gate electrode layer 350 over region 204A, [0033]) on the second body (Fig 12 semiconductor layer 215 over region 204B, [0030]) of semiconductor material (semiconductor, [0030]); wherein the dielectric structure (Fig 12 dielectric lines 414, [0047]) is between and separates (Fig 12) the first (Fig 12 gate electrode layer 350 over region 204A, [0033]) and second gate structures (Fig 12 gate electrode layer 350 over region 204A, [0033]).
Examiner notes the limitation of the dielectric structure separating the gate electrode does not require complete separation.
Regarding claim 19, Liaw teaches the dielectric structure (Fig 12 dielectric lines 414, [0047]) is above the PN junction (Fig 12).
Regarding claim 20, Liaw teaches an integrated circuit structure (Fig 10 GAA device 200, [0023]), comprising: a sub-fin (Fig 12 regions 204A/B, [0026]) including (i) a first portion (Fig 12 left region 204B, [0027]) comprising a first type of dopant (n-type, [0027]), (ii) a second portion (Fig 12 right region 204B, [0027]) comprising the first type of dopant (n-type, [0027]), and (iii) a third portion (Fig 12 region 204A, [0027]) comprising a second type of dopant (p-type, [0027]) different from the first type of dopant (n-type, [0027]); and a first diffusion region (Fig 13 source/drain feature 260A, [0030]) in contact with the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]), a second diffusion region (Fig 13 source/drain feature 260B, [0030]) in contact with the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]), and a third diffusion region (Fig 13 source/drain feature 260A, [0030]) in contact with the third portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); wherein the third portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) is laterally between the first (Fig 12 left region 204B, [0027]) and second portions (Fig 12 right region 204B, [0027]) of the sub-fins (Fig 12 regions 204A/B, [0026]), wherein the third portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]) is (i) in contact with the first portion (Fig 12 region 204A, [0027]) of the sub- fin, to form a first PN junction (Fig 12 left PN junction) between the third (Fig 12 region 204A, [0027]) and first portion (Fig 12 left region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026])s, and (ii) in contact with the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]), to form a second PN junction (Fig 12 right PN junction) between the third (Fig 12 region 204A, [0027]) and second portions (Fig 12 right region 204B, [0027]) of the sub-fins (Fig 12 regions 204A/B, [0026]).
Regarding claim 21, Liaw teaches the first (Fig 13 source/drain feature 260B, [0030]) and second diffusion regions (Fig 13 source/drain feature 260B, [0030]) comprise the first type of dopants (p-type, [0030]), and wherein the third diffusion region (Fig 13 source/drain feature 260A, [0030]) comprises the second type of dopants (n-type, [0030]).
Regarding claim 22, Liaw teaches a first body (Fig 12 semiconductor layer 215 over left region 204B, [0030]) of semiconductor material (semiconductor, [0030]) above the first sub-fin (Fig 12 regions 204A/B, [0026]) and extending (as a three-dimensional material there will be some extension) from the first diffusion region (Fig 13 source/drain feature 260A, [0030]); a second body (Fig 12 semiconductor layer 215 over right region 204B, [0030]) of semiconductor material (semiconductor, [0030]) above the second sub-fin (Fig 12 regions 204A/B, [0026]) and extending (as a three-dimensional material there will be some extension) from the second diffusion region (Fig 13 source/drain feature 260B, [0030]); and a third body (Fig 12 semiconductor layer 215 over region 204A, [0030]) of semiconductor material (semiconductor, [0030]) above the third sub-fin (Fig 12 regions 204A/B, [0026]) and extending (as a three-dimensional material there will be some extension) from the third diffusion region (Fig 13 source/drain feature 260A, [0030]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 7, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20240387674 A1), in view of Li et. al. (US 20160056147 A1), hereinafter Li.
Regarding claim 2, Liaw teaches a first diffusion region (Fig 13 source/drain feature 260A, [0030]) in contact with the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); and a second diffusion region (Fig 13 source/drain feature 260B, [0030]) in contact with the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); wherein the first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) extends from the first diffusion region (Fig 13 source/drain feature 260A, [0030]) towards (See annotated figure; Fig 1 was chosen because it also shows first and second portions) the second diffusion region (Fig 13 source/drain feature 260B, [0030]), and wherein the second body (Fig 12 semiconductor layer 215 over region 204B, [0030]) extends from the (See annotated figure; Fig 1 was chosen because it also shows first and second portions) second diffusion region (Fig 13 source/drain feature 260B, [0030]) towards the first diffusion region (Fig 13 source/drain feature 260A, [0030]).
Liaw fails to teach the first diffusion region comprising p-type dopant and the second diffusion region comprising n-type dopant.
However, Li teaches the desirability of large ESD devices to reduce damage to circuitry that are also space saving ([0008]). Further, Li teaches p-type and n-type regions may be constructed in areas of the substrate in which diodes are to be formed (Fig 3, [0028]). Additionally, Li teaches fins in different p-type and n-type regions, where the wells form diodes, in the well-to-well substrate, when the fins have the same doping type as the well region (Fig 5, [0039]). One having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to provide ESD protection to the finFETs of Liaw and in doing so would have placed a finFET of a first dopant type on a well of the same dopant type next to a finFET of a second dopant type on a well of the same second dopant type, the result of which would have been predictable. Thus, by combining the ESD protection fin/substrate doping arrangement of Li with the finFETs of Liaw the structure of the claimed invention would be realized. MPEP 2143(I)(G)
In modifying the finFETs of Liaw with the arrangement of Li, the first diffusion region (Fig 13 source/drain feature 260A, [0030]) would comprise a p-type dopant (p-type, [0201]) and the second diffusion region (Fig 13 source/drain feature 260B, [0030]) would comprise a n-type dopant (n-type, [0027]).
Examiner notes the source/drain features 260A/B are grown from the semiconductor layers 215. Thus, the semiconductor layers would still remain inside of the source/drain features after being grown ([0030]).
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Regarding claim 3, Liaw as modified in claim 2 teaches the first (Fig 12 semiconductor layer 215, [0030]) and second bodies (Fig 12 semiconductor layer 215, [0030]) of semiconductor material (semiconductor, [0030]) are each a fin or a nanoribbon (nanosheet, [0032]).
Regarding claim 4, Liaw as modified in claim 2 teaches a dielectric structure (Fig 12 dielectric lines 414, [0047]) laterally between and separating (Fig 12) the first (Fig 12 semiconductor layer 215, [0030]) and second bodies (Fig 12 semiconductor layer 215, [0030]).
Regarding claim 5, Liaw as modified in claim 4 teaches a first gate structure (Fig 9 dummy gate line 240IP over region 204A, [0045]) on the first body (Fig 12 semiconductor layer 215 over region 204A, [0030]) of semiconductor material (semiconductor, [0030]); and a second gate structure (not shown, dummy gate line 240IN over region 204B, [0045]) on the second body (Fig 12 semiconductor layer 215 over region 204B, [0030]) of semiconductor material (semiconductor, [0030]); wherein the dielectric structure (Fig 12 dielectric lines 414, [0047]) is laterally between and separates the first (Fig 12 gate electrode layer 350 over region 204A, [0033]) and second gate structures (Fig 12 gate electrode layer 350 over region 204A, [0033]).
Examiner notes the limitation of the dielectric structure separating the gate electrode does not require complete separation.
Regarding claim 7, Liaw as modified in claim 4 teaches the dielectric structure (Fig 12 dielectric lines 414, [0047]) is above the PN junction (Fig 12).
Regarding claim 14, Liaw teaches a first plurality of diffusion regions (Fig 13 source/drain feature 260A, [0030]) in contact with the first portion (Fig 12 region 204A, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); a second plurality of diffusion regions (Fig 13 source/drain feature 260B, [0030]) in contact with the second portion (Fig 12 region 204B, [0027]) of the sub-fin (Fig 12 regions 204A/B, [0026]); wherein a first number of diffusion regions within the first plurality of diffusion regions (Fig 13 source/drain feature 260A, [0030]) is different (Examiner interprets the source/drain features of 260A to be formed of two layers; thus, there are twice as many source/drain features 260A compared to source/drain features 260B) from a second number of diffusion regions within the second plurality of diffusion regions (Fig 13 source/drain feature 260B, [0030]).
Liaw fails to teach the first plurality of diffusion regions comprising p-type dopant and the second plurality of diffusion regions comprising n-type dopant.
However, Li teaches the desirability of large ESD devices to reduce damage to circuitry that are also space saving ([0008]). Further, Li teaches p-type and n-type regions may be constructed in areas of the substrate in which diodes are to be formed (Fig 3, [0028]). Additionally, Li teaches fins in different p-type and n-type regions, where the wells form diodes, in the well-to-well substrate, when the fins have the same doping type as the well region (Fig 5, [0039]). One having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to provide ESD protection to the finFETs of Liaw and in doing so would have placed a finFET of a first dopant type on a well of the same dopant type next to a finFET of a second dopant type on a well of the same second dopant type, the result of which would have been predictable. Thus, by combining the ESD protection fin/substrate doping arrangement of Li with the finFETs of Liaw the structure of the claimed invention would be realized. MPEP 2143(I)(G)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20240387674 A1), in view of Li et. al. (US 20160056147 A1), hereinafter Li, in further view of Mehandru et. al. (US 20200006559 A1), hereinafter Mehandru.
Liaw as modified in claim 5 teaches each of the first (Fig 9 dummy gate line 240IP over region 204A, [0045]) and second gate structures (not shown, dummy gate line 240IN over region 204B, [0045]).
Liaw as modified in claim 5 fails to teach the gate structures are electrically floating and lacks a corresponding gate contact.
However, Mehandru teaches a floating gate structure (Fig 10A isolation structure 380, [0073]) for use as an isolation structure ([0073]). Liaw teaches dummy gates as an isolation structure ([0034]). However, the dummy gates are tied to a voltage potential ([0045]). One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that regardless of whether the dummy gates are tied to a potential (Liaw) or floating (Mehandru) they would provide the same isolating function, as they do not take part in the circuit and are known in the art. MPEP 2143(I)(B)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xie et. al. (US 20230378258 A1) teaches a sub-fin with the PN junction being stacked vertically instead of side-to-side. The limitations can read on the structure.
Okubo (US 20190081032 A1) teaches a transistor region with a similar PN junction structure underneath the transistors. However, there is a diode region that is formed in a separate region.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813