CTFR 17/943,915 CTFR 85787 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment The following office action is in response to the amendment and remarks filed on 6/30/26. Applicant’s amendment to claims 1, 11, 20 and 24 is acknowledged. Claims 16 and 23 are cancelled. Claims 1-15, 17-22, 24 and 25 are pending and claims 12 and 20-22 are withdrawn. Claims 1-11, 13-15, 17-19, 24 and 25 are subject to examination at this time. Response to Arguments 07-38 Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. There is insufficient antecedent basis for “the seed layer”. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-5, 9-11, 15, 17, 19, 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al., US Publication No. 2013/0309813 A1 (of record) in view of Jeng et al., US Patent No. 11,443,993 (of record) . Shih teaches: 1. An interposer, comprising (see fig. 4): a substrate (10) with a first surface and a second surface opposite from the first surface,… a cavity (e.g. cavity U-shape in substrate 10)…from the first surface of the substrate; a via (20) through…the substrate, the via below the cavity; a first pad (12) in the cavity over the via (20); and a second pad (e.g. RDL or UBM per Remarks below) on the second surface of the substrate under the via. Regarding claim 1: In a first interpretation, Shih teaches a second pad such as RDL that couples via 20 to bump 38. See Shih at para. [0021] . In a second interpretation, Shih teaches a second pad such as a UBM layer that couples via 20 to bump 38. See Shih at para. [0020] and UMB (37) in fig. 1G. Shih does not expressly teach: wherein the substrate comprises glass, the glass continuous form the first surface to the second surface of the substrate; a cavity into the glass…; a via through the glass…; Shih teaches substrate 100 is an “interposer wafer” at para. [0015]. In an analogous art, Jeng teaches an interposer substrate (110 in figs. 1G and 5) may be made of glass material. See Jeng at col 4, ln 36–62. Specifically, Jeng teaches: (see figs. 1G and 5) wherein the substrate (110) comprises glass, the glass continuous form the first surface to the second surface of the substrate; a cavity (118) into the glass from the first surface of the substrate; a via (111) through the glass of the substrate, the via below the cavity. See Jeng at col 4-5, ln 1–67, col 7, ln 45–67 , col 16, ln 1–67. Regarding claim 2: Shih further teaches: 2. The interposer of claim 1, wherein the first pad (12) is coupled to a bridge (22) in the cavity, fig. 4. Regarding claim 3: In the embodiment shown in fig. 4, Shih does not expressly teach a second via in the bridge. However, it would have been obvious to one of ordinary skill in the art to form a second via in the bridge because Shih teaches an embodiment in fig. 6 “wherein a second via (60) passes through a thickness of the bridge (22)”. Regarding claim 4: Shih teaches the bridge (22) couples a first die (44), fig. 4 Shih does not expressly teach the bridge couples a first die to a second die. Jeng further teaches: (see fig. 5) wherein the bridge (504) couples a first die (506 left) to a second die (508 right), col 16, ln 1–67. Regarding claim 5: Jeng further teaches: wherein the first die is a photonics integrated circuit (PIC), and wherein the second die is a compute die, col 13, ln 25–50 . Regarding claim 9: Shih further teaches: 9. The interposer of claim 1, wherein the via (20) has vertical sidewalls or tapered sidewalls, fig. 4. Regarding claim 10: Jeng teaches a glass substrate as applied to claim 1 above. Shih and Jeng do not expressly teach the substrate comprises borosilicate glass or fused silica glass. However, it would have been obvious to one having ordinary skill in the art to form the glass substrate to comprise borosilicate glass or fused silica glass, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin , 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose. Regarding claim 11: Shih and Jeng teach the limitations as applied to claims 1 and 2 above. The recited “protrusion” corresponds to the to the first pad (12) in Shih’s fig. 4. Regarding claim 15: Shih teaches the limitations as applied to claim 1 above. Regarding claim 17: Shih teaches the limitations as applied to claim 6 above. Regarding claim 19: Shih further teaches: In the embodiment shown in fig. 4, Shih does not expressly teach a solder bump couples the protrusion to the bridge. . However, it would have been obvious to one of ordinary skill in the art to form a solder bump couples the protrusion to the bridge because Shih teaches an embodiment in fig. 6 wherein a solder bump (64) couples the protrusion (12) to the bridge (22). Regarding claim 24: Shih and Jeng teach the limitations as applied to claims 1, 2 and 4 above. Shih further teaches: 24. An electronic system, comprising: a board (50 in fig. 1G); an interposer(10) coupled to the board,.. wherein the pad (e.g. RDL at para. [0021] or UBM 37 in fig. 1G) is coupled to the board (50) by an interconnect (38). Regarding claim 25: Shih teaches the limitations as applied to claim 5 above. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shih with the teachings of Jeng because (i) One of ordinary skill in the art would be motivated to look for alternative materials for the interposer substrate and Jeng teaches glass is a known material suitable for an interposer substrate. Also see MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose; (ii) “in FIG. 5, the semiconductor device 504 received in the cavity 502 is electrically connected to a semiconductor device 506 stacked over the interposer substrate 110 and the interposer substrate 110 itself at the same time. Accordingly, the electrical performance of the overall package structure is further improved.” (e.g. Jeng at col 16, ln 35–40 ); and (iii) “Accordingly, the RC delay and/or signal noise are significantly reduced, and the signal transmission speed is improved.” (e.g. Jeng at col 15, ln 45–65 ) . 07-22-aia AIA Claim (s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Jeng , as applied to claim 1 above, and further in view of Duh et al., US Publication No. 2012/0181691 A1 (of record) . Regarding claim 6: Shih and Jeng teach all the limitations of claim 1 above, but do not expressly teach: wherein the second pad is covered by a surface finish layer. In an analogous art, Duh teaches a pad (211, 213) is covered by a surface finish layer (22, 23). See Duh at para. [0046] – [0054] , figs. 2-3. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shih with the teachings of Duh to form “wherein the second pad is covered by a surface finish layer” because “… the surface finish method applied in a package structure, a packaging substrate and a chip has advantages of simple manufacture, low cost and high reliability.” See Duh at Abstract . 07-22-aia AIA Claim (s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Jeng , as applied to claim 1 above, and further in view of Goto et al., US Publication No. 2023/0070624 A1 (of record) . Regarding claim 7: Shih and Jeng teach all the limitations of claim 1 above, but do not expressly teach: a solder resist over the second surface of the substrate, wherein an opening is formed through the solder resist to expose the second pad. In an analogous art, Goto teaches: (see figs. 6E-6F) a solder resist (4) over a second surface of the substrate (10/2/3/23/33), wherein an opening (4a) is formed through the solder resist to expose a second pad (3B). See Goto at para. [0050] – [0053]. Regarding claim 8: Shih and Jeng do not expressly teach: wherein an interface layer is provided between the second pad and the solder resist. Goto further teaches: (see figs. 6E-6F) wherein an interface layer (3P) is provided between a second pad (3B) and a solder resist (4). See Goto at para. [0050] – [0053]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shih with the teachings of Goto to because (i) The solder resist masks the substrate to enable the deposition of an interface/protective layer on the pad; and (ii) “The protective layer (3P) is, for example, a coating film formed for corrosion prevention and/or rust prevention of exposed portions such as the upper surface and the side surface of the pad body (3B)” See Goto at para. [0036] . 07-22-aia AIA Claim (s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view Jeng , as applied to claim 1 above, and further in view of Chao et al., US Publication No. 2010/0289133 A1 . Regarding claims 13 and 14: Shih and Jeng teach all the limitations of claim 1 above, but do not expressly teach: further comprising: a seed layer on sidewalls of the via. wherein the seed layer extends up the protrusion. In an analogous art, Chao teaches: further comprising (see figs. 10, 15-16): a seed layer (43) on sidewalls of the via (351). wherein the seed layer (43) extends up the protrusion (e.g. portions of layer 44 that extends outside the via 351 in fig. 15). See Chao at para. [0019] – [0025] . It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shih with the teachings of Chao because a seed layer can facilitate electro-plating of a conductor in the via (e.g. See “plating” in Abstract); and “The plating through hole 36 and the circuit layer 37 enable the packages 3, 4, 5 to have more input/output pads 371, and reduce the total thickness of the packages…” (e.g. Chao at para. [0028] . 07-22-aia AIA Claim (s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view Jeng , as applied to claim 1 above, and further in view of Mitarai, US Patent No. 2025/0254790 A1 (of record) . Regarding claim 18: Shih and Jeng teach all the limitations of claim 1 above, but do not expressly teach: wherein the via has tapered sidewalls. In an analogous art, Mitarai teaches a via (H) has tapered sidewalls in fig. 9, para. [0085] – [0087]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shih with the teachings of Mitarai because “…stress concentration decreases between a second core wiring 22 (see FIG. 1) and the opening edge of the through hole H, which is desirable from the viewpoint of reliability”. See Mitarai at para. [0085]. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 2 September 2026 Application/Control Number: 17/943,915 Page 2 Art Unit: 2818 Application/Control Number: 17/943,915 Page 3 Art Unit: 2818 Application/Control Number: 17/943,915 Page 4 Art Unit: 2818 Application/Control Number: 17/943,915 Page 5 Art Unit: 2818 Application/Control Number: 17/943,915 Page 6 Art Unit: 2818 Application/Control Number: 17/943,915 Page 7 Art Unit: 2818 Application/Control Number: 17/943,915 Page 8 Art Unit: 2818 Application/Control Number: 17/943,915 Page 9 Art Unit: 2818 Application/Control Number: 17/943,915 Page 10 Art Unit: 2818
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