DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 1/20/26. Currently, 1-19 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9-15, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over PENDSE (US PGPub 2012/0223428, hereinafter referred to as “Pendse”) in view of Pu et al. (US PGPub 2008/0224283, hereinafter referred to as “Pu”).
Pendse discloses the semiconductor method substantially as claimed. See figures 1A-5D and corresponding text, where Pendse teaches, in claim 9, a method of electrically coupling a semiconductor die to a leadframe (figure 12a), the method comprising:
forming a plurality of tapered bumps (290) on the semiconductor
die, such that each tapered bump of the plurality of tapered bumps has a first end surface area a1 at a first end (vertical top-surface of 290) and a second end surface area a2 at a second opposing end (vertical bottom-surface of 290), wherein the first end surface area al is less than the second end surface area a2, and wherein the first end is attached to the semiconductor die; and
soldering the second end of each tapered bump of the plurality of tapered bumps to the leadframe (285; [0119])
Pendse fails to explicitly show, in claim 9, wherein the plurality of tapered bumps is in a plurality of rows on the semiconductor die, and wherein a size of a tapered bump in a first row is different from a size of a tapered bump in a second row.
Pu teaches, in claim 9, wherein the plurality of tapered bumps (33, 34) is in a plurality of rows on the semiconductor die (Fig. 3A), and wherein a size of a tapered bump in a first row is different from a size of a tapered bump in a second row (33, 34; Fig. 3A). In addition, Pu provides the advantages of increasing the number of I/O connections and enhancing heat dissipating efficiency ([0008-0009]).
Therefore, it would have been obvious to one of ordinary skill in the art a before the effective filing date of the claimed invention, incorporate wherein the plurality of tapered bumps is in a plurality of rows on the semiconductor die, and wherein a size of a tapered bump in a first row is different from a size of a tapered bump in a second row, in the method of Pendse, according to the teachings of Pu, with the motivation of increasing the number of I/O connections and enhancing heat dissipating efficiency.
Pendse in view of Pu teaches, in claim 10, wherein the second end surface area a2 is at least twice the first end surface area a1. (figure 3A and 3B;[0029-0035], Pu)
Pendse in view of Pu teaches, in claim 11, wherein the plurality of tapered bumps has a sidewall slope of approximately 70 degrees or less with respect to a surface of the semiconductor die facing the leadframe. (12A; [0119]), Pendse
Pendse in view of Pu teaches, in claim 12, wherein each tapered bump of the plurality of tapered bumps has an oval shape in a lateral cross section that is orthogonal to a centerline of each tapered bump of the plurality of tapered bumps. (figures 12a; [0119], Pendse)
Pendse in view of Pu teaches, in claim 13, further comprising covering portions of the semiconductor die, the leadframe, and the plurality of tapered bumps using a mold compound. (298, [0127])
Pendse in view of Pu teaches, in claim 14, wherein the leadframe is metallic. (285; [0119], Pendse)
Pendse in view of Pu teaches, in claim 15, wherein the plurality of tapered bumps comprises copper. (285; [0119], Pendse)
Pendse in view of Pu teaches, in claim 18, wherein the tapered bump in the first row is a power bump and the tapered bump in the second row is a signal bump. (figure 3A and 3B;[0029-0035], Pu)
Pendse in view of Pu teaches, in claim 19, wherein the size of the tapered bump in the first row is greater than the size of the tapered bump in the second row. ((figure 3A and 3B;[0029-0035], Pu)
REASONS FOR ALLOWANCE
Claims 1-8, 16, and 17 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance:
the closest prior art of record based on Applicant’s persuasive arguments and after the Examiner’s further consideration and/or search does not suggest or render obvious a method of forming a semiconductor package, particularly characterized by, wherein each tapered bump of the plurality of tapered bumps has a first surface area a1 at a first end closest to the wafer and has a second surface area a2 at a second end further from the wafer, and wherein the first surface area a1 is less than the second surface area a2, as detailed in claim 1. Claims 2-8, 16 and 17 depend from claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, see Remarks, filed 1/20/26, with respect to the rejection(s) of claim(s) 9-15, 18 and 19 under 35 U.S.C. 103 as being unpatentable over Lee (US PGPub 2009/0152719, hereinafter referred to as “Lee”) in view of Lin et al. (US PGPub 2013/0069225, hereinafter referred to as “Lin”) in further view of Tseng et al. (US PGPub 2014/0167253, hereinafter referred to as “Tseng”) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of under 35 U.S.C. 103 as being unpatentable over PENDSE (US PGPub 2012/0223428, hereinafter referred to as “Pendse”) in view of Pu et al. (US PGPub 2008/0224283, hereinafter referred to as “Pu”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STANETTA D ISAAC/Examiner, Art Unit 2898 May 12, 2026
Prosecution Insights