DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 9/12/2025 have been fully considered but they are not persuasive.
Examiner would like to point to the interview summary mailed 8/6/2025 where Examiner stated that the use of terms “regions and portion of an electrode” is broad and that portions of the electrode of the Kim reference could be arbitrarily chosen to meet any claim limitation that does not specify the entirety of a particular surface.
Therefore when Applicant argues on page 11 that claim 1, and similarly in claim 9, recites “wherein a lower surface of a portion of the first upper electrode overlapping the first cup shape is flat” is not taught by Kim. Examiner respectfully disagrees. Since the bottom-most portion of the upper electrode P’ which overlaps the first cup shape, and since this portion is flat, Examiner believes the amended claims still do not distinguish over the prior art.
The rejection is being maintained and has been updated to include the amended portions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US PGPub 2013/0026551) in view of Jang et al. (US PGPub 2012/0001272; hereinafter “Jang”).
Re claim 1: Kim teaches (e.g. fig. 16) a semiconductor device comprising: a substrate (351) including a cell region (region labeled “Cell” in fig. 16; hereinafter “CR”) and a peripheral circuit region (region labeled “Peri” in fig. 16; hereinafter “PR”); gate structures (element labeled “Gate” of transistor Tr; hereinafter “GS”) on the cell region (CR) of the substrate (351); bit line structures (element labeled “BL” of transistor Tr; hereinafter “BL”) on the cell region (CR) of the substrate (351); contact plug structures (plug to the right of GS; hereinafter “CPS”) disposed in the second direction (right-left direction of fig. 16) between the bit line structures (BL) on the substrate (351); first capacitors (capacitor C above CPS; hereinafter “1C”) on the contact plug structures (CPS), respectively; a conductive pad (SNC1, SNC2) on the peripheral circuit region (PR) of the substrate (351), the conductive pad (SNC1, SNC2) being electrically insulated from the substrate (351); and second capacitors (31, 33) on the conductive pad (SNC1, SNC2), the second capacitors (31, 33) being arranged in the first (into-out of direction of fig. 16) and second (right-left direction of fig. 16) directions, wherein: each of the first capacitors (1C) includes: a first lower electrode (SN’, SNC’; hereinafter “1LE”) having a first cup shape (1LE has a cup shape); a first dielectric pattern (358 of 1C) on a surface of the first lower electrode (1LE), the first dielectric pattern (358 of 1C) filling an inner space of the first cup shape of the first lower electrode (1LE); and a first upper electrode (P’) on a surface of the first dielectric pattern (358 of 1C), and each of the second capacitors (31, 33) includes: a second lower electrode (SN of 31, 33; hereinafter “2LE”) having a second cup shape (shape of 2LE is cup-shaped); a second dielectric pattern (358 of 31, 33) on a surface of the second lower electrode (2LE); and a second upper electrode (P) on a surface of the second dielectric pattern (358 of 31, 33), wherein the second dielectric pattern (358 of 31, 33) and the second upper electrode (P) fill an inner space of the second cup shape of the second lower electrode (2LE), wherein a lower surface (lower surface of P’) of a portion (portion of P’ within the cup shape of 1LE) of the first upper electrode (P’) overlapping the first cup shape (cup shape of 1LE) is flat (a portion of the lower surface of P’ is flat).
Kim is silent as to explicitly teaching each of the gate structures extending in a first direction substantially parallel to an upper surface of the substrate; each of the bit line structures extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction.
Jang teaches (e.g. figs. 1 and 2A) each of the gate structures (222) extending in a first direction (x-direction of fig. 1) substantially parallel to an upper surface of the substrate (110); each of the bit line structures (bit line structures 300; e.g. paragraph 46) extending in a second direction (z-direction of fig. 1) substantially parallel to the upper surface of the substrate and crossing the first direction (x-direction of fig. 1).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results to use the cell region details of a DRAM device as taught by Jang in the device of Kim in order to have the predictable result of simplifying design by using a known DRAM cell arrangement forming an operable DRAM device.
Re claim 2: Kim teaches the semiconductor device according to claim 1, wherein a width of the second cup shape of the second lower electrode (2LE) is greater than (C1 of 33 has a greater width than 1C) a width of the first cup shape of the first lower electrode (1LE).
Claim(s) 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang, and Kim (US PGPub 2016/0336311; hereinafter “Kim2”), as evidenced by Nam et al. (US PGPub 2006/0186452).
Re claim 9: Kim teaches (e.g. fig. 16) a semiconductor device comprising: a substrate (351) including a cell region (region labeled “Cell” in fig. 16; hereinafter “CR”) and a peripheral circuit region (region labeled “Peri” in fig. 16; hereinafter “PR”); gate structures (element labeled “Gate” of transistor Tr; hereinafter “GS”) on the cell region (CR) of the substrate (351); bit line structures (element labeled “BL” of transistor Tr; hereinafter “BL”) on the cell region (CR) of the substrate (351); contact plug structures (plug to the right of GS; hereinafter “CPS”) disposed in the second direction (right-left direction of fig. 16) between the bit line structures (BL) on the substrate (351); first capacitors (capacitor C above CPS; hereinafter “1C”) on the contact plug structures (CPS), respectively; a conductive pad (SNC1, SNC2) on the peripheral circuit region (PR) of the substrate (351), the conductive pad (SNC1, SNC2) being electrically insulated from the substrate (351); and second capacitors (31, 33) on the conductive pad (SNC1, SNC2), the second capacitors (31, 33) being arranged in the first (into-out of direction of fig. 16) and second (right-left direction of fig. 16) directions, wherein: each of the first capacitors (1C) includes: a first lower electrode (SN’, SNC’; hereinafter “1LE”) having a first cup shape (1LE has a cup shape); a first dielectric pattern (358 of 1C) on a surface of the first lower electrode (1LE); a first upper electrode (P’) on a surface of the first dielectric pattern (358 of 1C); and each of the second capacitors (31, 33) includes: a second lower electrode (SN of 33; hereinafter “2LE”) having a second cup shape (shape of 2LE is cup-shaped); a second dielectric pattern (358 of 31, 33) on a surface of the second lower electrode (2LE); a second upper electrode (P) on a surface of the second dielectric pattern (358 of 31, 33); and wherein the second dielectric pattern (358 of 31, 33), the second upper electrode (P) fill an inner space of the second cup shape of the second lower electrode (2LE), wherein a lower surface (lower surface of P’) of a portion (portion of P’ within the cup shape of 1LE) of the first upper electrode (P’) overlapping the first cup shape (cup shape of 1LE) is flat (a portion of the lower surface of P’ is flat).
Kim is silent as to explicitly teaching each of the gate structures extending in a first direction substantially parallel to an upper surface of the substrate in the cell region; each of the bit line structures extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction.
Jang teaches (e.g. figs. 1 and 2A) each of the gate structures (222) extending in a first direction (x-direction of fig. 1) substantially parallel to an upper surface of the substrate (110); each of the bit line structures (bit line structures 300; e.g. paragraph 46) extending in a second direction (z-direction of fig. 1) substantially parallel to the upper surface of the substrate and crossing the first direction (x-direction of fig. 1).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results to use the cell region details of a DRAM device as taught by Jang in the device of Kim in order to have the predictable result of simplifying design by using a known DRAM cell arrangement forming an operable DRAM device.
Kim in view of Jang is silent as to teaching a third upper electrode on a surface of the first upper electrode ; and a fourth upper electrode on a surface of the second upper electrode
Kim2 teaches (e.g. fig. 4) a third upper electrode (capacitor electrode second layer 219B made of SiGe; e.g. paragraph 65) on a surface of the first upper electrode (capacitor electrode first layer 219A made of TiN; e.g. paragraph 65); and a fourth upper electrode (capacitor electrode second layer 116B made of SiGe; e.g. paragraph 38) on a surface of the second upper electrode (capacitor electrode first layer 116A made of TiN; e.g. paragraph 38).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the multi-layer capacitor electrodes for a DRAM capacitor as taught by Kim2 in the device of Kim in view of Jang in order to have the predictable result of using known capacitor electrodes which would have decreased leakage current and improving device efficiency (see paragraph 42 and fig. 9 of Nam).
Re claim 10: Kim teaches the semiconductor device according to claim 9, wherein a width of the second cup shape of the second lower electrode (2LE) is greater than (C1 of 33 has a greater width than 1C) a width of the first cup shape of the first lower electrode (1LE).
Re claim 11: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 9, wherein: the first lower electrodes (1LE of Kim) included in the first capacitors (1C of Kim) are arranged in a honeycomb pattern or a lattice pattern in a plan view (see fig. 1 of Jang), wherein the first dielectric pattern (358 of 1C of Kim), the first upper electrode (P’ of Kim, 219A of Kim2) and the third upper electrode (219B of Kim2) included in the first capacitors (1C of Kim) are commonly formed on the first lower electrodes (SN’ of Kim, 217 of Kim2).
Re claim 12: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 9, wherein: the second lower electrodes (2LE of Kim, 114 of Kim2) included in the second capacitors (33 of Kim) are arranged in a honeycomb pattern or a lattice pattern in a plan view (see fig. 1 of Jang), wherein the second dielectric pattern (358 of 33 of Kim), the second upper electrode (P of Kim, 116B of Kim2) and the fourth upper electrode (116B of Kim2) included in the second capacitors (33 of Kim) are commonly formed on the second lower electrodes (2LE of Kim).
Re claim 13: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 12, wherein: the conductive pad (SNC1, SNC2 of Kim) includes a plurality of conductive pads spaced apart from each other (SNC1, SNC2 of Kim are spaced apart) on the peripheral circuit region (PR of Kim) of the substrate (351 of Kim), wherein the second dielectric pattern (358 of 33 of Kim), the second upper electrode (P of Kim, 116B of Kim2) and the fourth upper electrode (116B of Kim2) are commonly formed on the second lower electrodes (SN of Kim) on a pair of conductive pads (SNC1, SNC2 of Kim) that are adjacent to each other among the plurality of conductive pads (SNC1, SNC2 of Kim).
Re claim 14: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 12, further comprising first and second wirings disposed on and electrically connected to the pair of conductive pads (SNC1, SNC2 of Kim), respectively, wherein a source voltage (H1) and a ground voltage (L) are applied to the first (wiring supplying H1 voltage to SNC2; e.g. paragraph 24 of Kim) and second (wiring supplying L voltage to SNC1) wirings, respectively.
Claim(s) 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang as applied to claim 1 above, and further in view of Kim (US PGPub 2016/0336311; hereinafter “Kim2”), as evidenced by Nam et al. (US PGPub 2006/0186452).
Re claim 3: Kim in view of Jang teaches substantially the entire structure as claimed in claim 1 except explicitly teaching the semiconductor device wherein: each of the first capacitors further includes a third upper electrode on the first upper electrode; and each of the second capacitors further includes a fourth upper electrode on the second upper electrode.
Kim2 teaches (e.g. fig. 4) each of the first capacitors (1C of Kim) further includes a third upper electrode (capacitor electrode second layer 219B made of SiGe; e.g. paragraph 65) on the first upper electrode (capacitor electrode first layer 219A made of TiN; e.g. paragraph 65); and each of the second capacitors (33 of Kim) further includes a fourth upper electrode (capacitor electrode second layer 116B made of SiGe; e.g. paragraph 38) on the second upper electrode (capacitor electrode first layer 116A made of TiN; e.g. paragraph 38).
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the multi-layer capacitor electrodes for a DRAM capacitor as taught by Kim2 in the device of Kim in view of Jang in order to have the predictable result of using known capacitor electrodes which would have decreased leakage current and improving device efficiency (see paragraph 42 and fig. 9 of Nam).
Re claim 4: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 3, wherein: each of the first and second upper electrodes (219A, 116A of Kim2) includes a metal nitride (TiN; e.g. paragraph 38 of Kim2); and each of the third and fourth upper electrodes (219B, 116B of Kim2) includes silicon-germanium doped with impurities (SiGe would include impurities since it acts as an electrode; e.g. paragraph 65 of Kim2).
Re claim 5: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 3, wherein: the first lower electrodes (1LE of Kim) included in the first capacitors (1C of Kim) are arranged in a honeycomb pattern or a lattice pattern in a plan view (see fig. 1 of Jang), wherein the first dielectric pattern (358 of 1C of Kim), the first upper electrode (P’ of Kim, 219A of Kim2) and the third upper electrode (219B of Kim2) included in the first capacitors (1C of Kim) are commonly formed on the first lower electrodes (SN’ of Kim, 217 of Kim2).
Re claim 6: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 3, wherein: the second lower electrodes (2LE of Kim, 114 of Kim2) included in the second capacitors (33 of Kim) are arranged in a honeycomb pattern or a lattice pattern in a plan view (see fig. 1 of Jang), wherein the second dielectric pattern (358 of 33 of Kim), the second upper electrode (P of Kim, 116B of Kim2) and the fourth upper electrode (116B of Kim2) included in the second capacitors (33 of Kim) are commonly formed on the second lower electrodes (2LE of Kim).
Re claim 7: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 6, wherein: the conductive pad (SNC1, SNC2 of Kim) includes a plurality of conductive pads spaced apart from each other (SNC1, SNC2 of Kim are spaced apart) on the peripheral circuit region (PR of Kim) of the substrate (351 of Kim), wherein the second dielectric pattern (358 of 33 of Kim), the second upper electrode (P of Kim, 116B of Kim2) and the fourth upper electrode (116B of Kim2) are commonly formed on the second lower electrodes (SN of Kim) on a pair of conductive pads (SNC1, SNC2 of Kim) that are adjacent to each other among the plurality of conductive pads (SNC1, SNC2 of Kim).
Re claim 8: Kim in view of Jang and Kim2 teaches the semiconductor device according to claim 7, further comprising first and second wirings disposed on and electrically connected to the pair of conductive pads (SNC1, SNC2 of Kim), respectively, wherein a source voltage (H1) and a ground voltage (L) are applied to the first (wiring supplying H1 voltage to SNC2; e.g. paragraph 24 of Kim) and second (wiring supplying L voltage to SNC1) wirings, respectively.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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