DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Response to Election/Restriction filed on 8/28/2025, IDS filed on 7/22/2024 and 9/15/2022 and Application filed on 9/15/2022. Claims 1-12 are pending, wherein claims 1-3,10-12 have been withdrawn from further consideration as being directed to non-elected invention without traverse as noted below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of group II invention, claims 4-9 in the reply filed on 8/28/2025 is acknowledged.
Claims 1-3,10-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 98/28/2025.
This application is in condition for allowance except for the presence of claims 1-3,10-12 directed to invention non-elected without traverse. Accordingly, claims 1-3,10-12 been cancelled as given the following Examiner’s amendment.
Applicant is again reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, wherein it is clear what is meant by “on a premise that the target virtual connection layer is NOT identified” (claim 4, lines 4-5) since the “selecting of any one virtual connection layer as a target virtual connection layer” (claim 4, line 4) would ensure that target connection layer is identified; also, it is not clear what is meant by “on a premise that the target virtual connection layer is identified” (claim 4, line 8) since the “selecting of any one virtual connection layer as a target virtual connection layer” (claim 4, line 4) would ensure that the target connection layer is identified. Additionally, the limitations that “on a premise that the target virtual connection layer is NOT identified” and “on a premise that the target virtual connection layer is identified” are directed to description of a problem to be solved or a function or result achieved by the invention, without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim; thus resulting in the claims being indefinite. That is, does the selecting step establish whether is the target virtual connection is or is not identified? If so, then Applicant needs to amend the claim to clearly so stated; else, Applicant needs to add a step that would practically perform this function. Without performing the necessary step(s) to ensure that the premise(s) is/are correct, the first and/or second results are meaningless. (See MPEP 2173.05(g); Federal Register, Vol. 76, No. 27, February 9, 2011, pp. 7164-7165). For examination purposes, these premises or presumptions do NOT give weight to the rest of the claims because these premises or presumptions are indefinite.
Claims 7-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, it is clear what is meant by “on a premise that the virtual connection is not identified” (claim 7, line 5) means since the “layout does NOT comprise a virtual connection layer” (claim 7, lines 3-4)-- does it imply that no virtual connection can be identified or does it mean that the virtual connection layer is not identified because of other conditions. Additionally, the limitations that “on a premise that the target virtual connection layer is NOT identified” is directed to description of a problem to be solved or a function or result achieved by the invention, without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim; thus resulting in the claims being indefinite as discussed above. Additionally, per claims 8-9, it is not understood what is meant by “on a premise that the virtual connection is identified” (claim 8, line 5) since the step of “connecting at least two ports using the virtual connection layer” (claim 8, line 3) would necessarily implied that the virtual connection layer is identified in order to connect the two ports using that virtual connection layer. Additionally, this limitation is directed to description of a problem to be solved or a function or result achieved by the invention, without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim; thus resulting in the claims being indefinite. Without performing the necessary step(s) to ensure that the premise(s) is/are correct, the first and/or second results are meaningless. (See MPEP 2173.05(g); Federal Register, Vol. 76, No. 27, February 9, 2011, pp. 7164-7165). For examination purposes, these premises or presumptions do NOT give weight to the rest of the claims because these premises or presumptions are indefinite as discussed above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 4-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al. (US Patent No. 8,972,916 B1).
As per claim 4, Fig. 3 illustrates the elements of the claim, wherein
the layout and a schematic are provided as 12-1..n netlist and 12-1..12.n layout, in which the layout comprises at least two ports having a same name (i.e., share ports—see col. 4, line 61 to col. 5, lines 34) , and wherein the layout comprises at least one virtual connection layer connecting two ports (i.e., the inter-chip connectivity, connected by the inter-layer ports or share ports (see col. 4, lines 52-66);
the layout versus schematic (i.e., LVS) is performed for the selected or corresponding target virtual connection layer (i.e., chip layer 12-1…12.n) (see col. 4, lines 52-67), wherein on the premise that the target virtual connection is not identified is at least covered the layout contains both correct virtual connections or incorrect virtual connections which have not been identified prior to running the LVS verification;
layout versus schematic (LVS) is performed again on a premise that the target virtual connection layer is identified (i.e., LVS check results in error, which results in which virtual connection layer being identified as connection error, port error, or property error) which are then corrected, after which another LVS is performed, until there is no error (i.e., no abnormality), the layout meets requirement (see col. 5, line 45 to col. 6, line 14; see also Fig. 6).
As per claim 5, as further taught in Fig. 3 and 6, when the first and second result indicates a virtual connection error or abnormality (i.e., no clean or LVS incorrect) during the any of the first LVS iteration or any of the second iteration, correction(s) is/are made, inter-layer ports are re-generated (i.e., connecting two ports or two other ports that need to be tested using the target connection layer) and LVS check is performed until there is no more error or meet requirements.
As per claim 6, as shown in Fig. 3, all of the virtual connection layers are traversed (i.e., chip connection layers 12-1..12-n corresponding to layout 12-1…12-n) which serves as the target virtual connection at least once during the LVS verification (see also Fig. 6).
As per claim 7, Fig. 3 illustrates the elements of the claim, wherein
the layout and a schematic are provided as 12-1..n netlist and 12-1..12.n layout, in which the layout comprises at least two ports having a same name (i.e., share ports—see col. 4, line 61 to col. 5, lines 34) , and wherein the layout does not comprise a virtual connection layer is when there is a possibility of violation in which there’s a connection error or missing port error (see col. 5, line 61 to col. 6, line 14
performing layout versus schematic comparison (shown in Fig. as LVS) to obtain a first result, wherein the limitations that “on a premise that the virtual connection layer is not identified” is at least covered by there is no virtual connection layer due to the possibility of violation, and if the result indicates no abnormality (i.e., clean—see col. 5, line 45 to col. 6, line 14), the layout meets the requirements.
As per claims 8-9, when the first result indicates a virtual connection error (i.e., incorrect), at least two ports or two other ports (i.e., share ports or inter-layer ports are created) are connected using the virtual connection layer, LVS is performed to get a subsequent (i.e., second or third) result (which are repeated) until the layout meets the requirements (i.e., the LVS check is correct) (see col. 5, line 45 to col. 6, line 14; see also Fig. 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHALLAKA KIK whose telephone number is (571)272-1895. The examiner can normally be reached Maxiflex Mon-Fri 8:30AM-5PM.
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Any response to this action should be mailed to:
Commissioner for Patents
P. O. Box 1450
Alexandria, VA 22313-1450
or faxed to:
571-273-8300
/PHALLAKA KIK/Primary Examiner, Art Unit 2851 November 14, 2025