Prosecution Insights
Last updated: October 02, 2026

Examiner: KIK, PHALLAKA

Tech Center 2800 • Art Units: 2825 2851

This examiner grants 91% of resolved cases

Analysis

Phallaka Kik, working in Tech Center 2800 and Art Unit 2825, maintains an allowance rate of 90.8 across 964 resolved cases. This rate suggests that the majority of applications reaching a final disposition result in a patent. The median days to allowance is 789, which establishes a timeline for applicants in this art unit. This 789-day figure is a benchmark for managing the prosecution schedule.

The interview lift is 1.6, indicating that interviews do not substantially change the 90.8 probability of allowance. With 964 resolved cases, the data provides a robust profile of an examiner who is generally inclined toward granting patents. Practitioners can focus on the quality of their submissions to align with the 90.8 baseline, using the 789-day median as a guide for pendency. The 1.6 lift suggests that verbal advocacy is a standard but not transformative part of the process.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

90.8%
Allow Rate
+22.8% vs TC avg
972
Total Applications
+1.6%
Interview Lift
789
Avg Prosecution Days
Based on 964 resolved cases, 2023–2026

Rejection Statute Breakdown

32.2%
§101 Eligibility
26.3%
§102 Novelty
16.7%
§103 Obviousness
9.2%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18518551 METHOD, APPARATUS, AND SYSTEM WITH RESIST IMAGE ESTIMATION Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18454957 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, STORAGE MEDIUM, EXPOSURE APPARATUS, EXPOSURE METHOD, AND ARTICLE MANUFACTURING METHOD Non-Final OA CANON KABUSHIKI KAISHA
18211165 PRE-SILICON POWER ANALYSIS Non-Final OA Intel Corporation
18209434 THERMAL CONDUCTIVITY IN INTEGRATED CIRCUITS Non-Final OA Intel Corporation
18527383 INSPECTION METHOD AND RELATED INSPECTION DEVICE FOR OUT-OF-ORDER EXECUTION CENTRAL PROCESSING UNIT CIRCUIT Non-Final OA Realtek Semiconductor Corp.
18526129 METHODS AND SYSTEMS FOR PROVIDING SHORT STRUCTURES FOR BACKDRILL VALIDATION Non-Final OA CIENA CORPORATION
18478469 RUNTIME OPTIMIZATION OF ACTIVE INTERPOSER DIES FROM DIFFERENCE PROCESS BINS Non-Final OA Advanced Micro Devices, Inc.
18217339 INTERPOSER STITCH THROUGH A TOP CHIPLET Non-Final OA XILINX, INC.
18211465 SYNTHESIS OF SIMULATION-DIRECTED STATEMENTS Non-Final OA Xilinx, Inc.

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