DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Applicant amended claims 1 and 10 in the reply dated 23 June 2026. Claims 17-20 were previously withdrawn.
Claim Objections
Claim 16 is objected to because of the following informalities: The word --the-- appears to be missing from the phrase “...laterally adjacent to first field effect transistor...”. This phrase has been changed to -- laterally adjacent to the first field effect transistor--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Smith (US 20230378170 a1, hereinafter “Smith”).
Regarding Claim 1 – Smith discloses a semiconductor structure comprising: a first field effect transistor (First in annotated Fig. 1B) comprising a first gate structure (115b [0147] and Fig. 1B), wherein the first gate structure has a first sidewall (FS1 in annotated Fig. 1B) and a second sidewall (SS1 in annotated Fig. 1B) opposite the first sidewall; a second field effect transistor stacked vertically on top of the first field effect transistor (Second in annotated Fig. 1B) and comprising a second gate structure (125b [0150] and Fig. 1B), wherein the second gate structure has a first sidewall (FS2 in annotated Fig. 1B) and a second sidewall (SS2 in annotated Fig. 1B) opposite the first sidewall, and wherein the first sidewall of the second gate structure is vertically aligned with the first sidewall of the first gate structure and the second sidewall of the second gate structure is vertically aligned with the second sidewall of the first gate structure (Annotated Fig. 1B); and a shunting material pillar (131g [0147] and Fig. 1B) located along, and in direct physical contact with at least one of the first sidewall of both the first gate structure and the second gate structure or the second sidewall of both the first gate structure and the second gate structure (As shown in Fig. 1B), wherein the shunting material pillar has a topmost surface that is coplanar with a topmost surface of the second gate structure (Top of 131g coplanar with 128b as shown in Fig. 1B).
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Regarding Claim 2 – Smith further discloses the semiconductor structure of Claim 1, wherein the shunting material pillar is located along the first sidewall of both the first gate structure and the second gate structure, and along the second sidewall of both the first gate structure and the second gate structure (131g on both sides of and directly contacting 128b and 118b as in Fig. 1B).
Regarding Claim 5 – Smith further discloses the semiconductor structure of Claim 1, wherein the shunting material pillar has a length that is equal to a length of both the first gate structure and the second gate structure (131g extends from the top of the second gate structure to the bottom of the first gate structure in Fig. 1B).
Regarding Claim 6 – Smith further discloses the semiconductor structure of Claim 1, wherein the shunting material pillar has a length that greater than a length of both the first gate structure and the second gate structure (131g may extend through 105a to reach backside power rails 141 [0147]).
Regarding Claim 7 – Smith further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is a first conductivity type and the second field effect transistor is of second conductivity type, and the second conductivity type is of a different conductivity than the first conductivity type (NMOS and PMOS stacked [0139]).
Regarding Claim 8 – Smith further discloses the semiconductor structure of Claim 7, wherein the first conductivity type is n-type, and the second conductivity type is p-type (The first tier may be either n-type or p-type [0149], and the second tier may be either n-type or p-type [0150]).
Regarding Claim 9 – Smith further discloses the semiconductor structure of Claim 7, wherein the first conductivity type is p-type, and the second conductivity type is n-type ([0189]).
Regarding Claim 10 – Smith further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is a first conductivity type and the second field effect transistor is of second conductivity type, and the second conductivity type is of a same conductivity as the first conductivity type (The first tier may be either n-type or p-type [0149], and the second tier may be either n-type or p-type [0150]).
Regarding Claim 11 – Smith further discloses the semiconductor structure of Claim 1, wherein the first gate structure comprises one of an n-type work function metal or a p-type work function metal, and the second gate structure comprises the other of the n-type work function metal or the p-type work function metal (The work function metal may be different [0154]).
Regarding Claim 12 – Smith further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is located above a bottom dielectric isolation layer (105a [0158] and Fig. 1A) that is present on a semiconductor substrate (147 [0143] and Fig. 1A).
Regarding Claim 13 – Smith further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is located in a first device region (110 [0143] and Fig. 1A), and the second field effect transistor is located in a second device region (120 [0143] and Fig. 1A), wherein the first device region is spaced apart from the second device region by a device separating dielectric material layer (105b [0158] and Fig. 1A).
Regarding Claim 14 – Smith further discloses the semiconductor structure of Claim 1, wherein the first gate structure wraps around each first semiconductor channel material nanosheet of a plurality of first semiconductor channel material nanosheets (e.g. 118B wraps around 111b [0149], [0154] and Fig. 1B), and the second gate structure wraps around each second semiconductor channel material nanosheet of a plurality of second semiconductor channel material nanosheets (e.g. 128B wraps around 121b [0150], [0154] and Fig. 1B).
Regarding Claim 15 – Smith further discloses the semiconductor structure of Claim 14, further comprising a first gate dielectric material layer separating the first gate structure from each first semiconductor channel material nanosheet of the plurality of first semiconductor channel material nanosheets (117b [0154] and Fig. 1B), and a second gate dielectric material layer separating the second gate structure from each second semiconductor channel material nanosheet of the plurality of second semiconductor channel material nanosheets (127b [0154] and Fig. 1B).
Regarding Claim 16 - Smith further discloses the semiconductor structure of Claim 1, further comprising at least one other stacked field effect transistor device located laterally adjacent to the first field effect transistor and the second field effect transistor, wherein the at least one other stacked field effect transistor device is devoid of a shunting material pillar (Other in annotated Fig. 55).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Smith (US 20230378170 A1, hereinafter “Smith”), in view of Smith et al (US 20210013111 A1, hereinafter “Smith2”).
Regarding Claim 3 – Smith discloses all the limitations of Claim 1.
Smith fails to expressly disclose the shunting material pillar has a resistivity that is lower than a resistivity of both the first gate structure and the second gate structure.
However, Smith2 specifies several work function metal, both p-type (TiN) and n-type (TiAl, TiAlN, and TiAlC) (Smith2 [0084] and [0086]), all of which have higher resistivity than cobalt, tungsten, or ruthenium mentioned as shunting material (Smith [0263]).
Material
Resistivity
Source
TiN
4750 nΩ m
Yun et al, “Electrical and Corrosion Properties of Titanium Aluminum Nitride Thin Films Prepared by Plasma-Enhanced Atomic Layer Deposition”, Journal of Materials Science & Technology, Volume 33, Issue 3, March 2017, Pages 295-299.
TiAl
Up to 420 nΩ m
https://www.periodic-table.org/titanium-electrical-resistivity/
TiAlN
28000 nΩ m
Yun et al, “Electrical and Corrosion Properties of Titanium Aluminum Nitride Thin Films Prepared by Plasma-Enhanced Atomic Layer Deposition”, Journal of Materials Science & Technology, Volume 33, Issue 3, March 2017, Pages 295-299.
TiAlC
10000+ nΩ m
Xiang et al, “Investigation of TiAlC by Atomic Layer Deposition as N Type Work Function Metal for FinFET”, ESC Journal of Solid State Science and Technology, Volume 4, Number 12, p 441.
Cobalt
62.4 nΩ m
https://www.periodic-table.org/cobalt-electrical-resistivity/
Tungsten
52.8 nΩ m
https://www.periodic-table.org/tungsten-electrical-resistivity/
Ruthenium
71 nΩ m
https://www.periodic-table.org/ruthenium-electrical-resistivity/
Smith2 discloses a similar nanosheet transistor structure to Smith with a low resistance metal contacting the work function metal around the channels. Smith2 specifies some of the work function metals, making it possible to compare the properties of the materials and see the disclosed shunting pillar will inherently have lower resistivity than the work function metals contacting the gate dielectrics. See MPEP 2112(III).
Regarding Claim 4 – Smith modified by Smith2 discloses all the limitations of Claim 3.
The combination of Smith and Smith2 further discloses the shunting material pillar is composed of cobalt, tungsten, or ruthenium (Smith [0263]).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571)272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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