DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the shunt length comparison to both first and second gate structures must be shown or the features canceled from the claims. Currently, only the upper structure (24) is shown in Figures 2A and 2B. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: STACKED TRANSISTORS WITH REDUCED GATE RESISTANCE.
Claim Objections
Claim 6 is objected to because of the following informalities: The word --is-- appears to be missing from the phrase --shunting material pillar has a length that greater than a length of both the first gate structure and the second gate structure--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chanemougame et al (US 20230017350 A1, hereinafter “Chanemougame”).
Regarding Claim 1 – Chanemougame discloses a semiconductor structure comprising: a first field effect transistor (First in annotated Fig. 8e) comprising a first gate structure (492 [0037] and Fig. 8e), wherein the first gate structure has a first sidewall (FS1 in annotated Fig. 8e) and a second sidewall (SS1 in annotated Fig. 8e) opposite the first sidewall; a second field effect transistor stacked vertically on top of the first field effect transistor (Second in annotated Fig. 8e) and comprising a second gate structure, wherein the second gate structure has a first sidewall (FS2 in annotated Fig. 8e) and a second sidewall (SS2 in annotated Fig. 8e) opposite the first sidewall, and wherein the first sidewall of the second gate structure is vertically aligned with the first sidewall of the first gate structure and the second sidewall of the second gate structure is vertically aligned with the second sidewall of the first gate structure (Annotated Fig. 8e); and a shunting material pillar (715 [0044] and Fig. 8e) located along at least one of the first sidewall of both the first gate structure and the second gate structure or the second sidewall of both the first gate structure and the second gate structure (As shown in Fig. 8e).
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Regarding Claim 5 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the shunting material pillar has a length that is equal to a length of both the first gate structure and the second gate structure (715 appears to be similar in length to the distance between the bottom end of contact 716 and the top of dielectric isolation 408 in Fig. 8e).
Regarding Claim 6 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the shunting material pillar has a length that greater than a length of both the first gate structure and the second gate structure (715 longer than FS1+SS1 or FS2+SS2 in Fig. 8e. Also, 715 could extend further into 712 as alluded to in [0044] to ensure overlap with the lower gate region).
Regarding Claim 7 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is a first conductivity type (n-type or p-type [0008]) and the second field effect transistor is of second conductivity type (n-type or p-type [0008]), and the second conductivity type is of a different conductivity than the first conductivity type (One n-type, and one p-type [0008]).
Regarding Claim 8 – Chanemougame further discloses the semiconductor structure of Claim 7, wherein the first conductivity type is n-type, and the second conductivity type is p-type ([0008]).
Regarding Claim 9 – Chanemougame further discloses the semiconductor structure of Claim 7, wherein the first conductivity type is p-type, and the second conductivity type is n-type ([0008]).
Regarding Claim 10 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is a first conductivity type and the second field effect transistor is of second conductivity type, and the second conductivity type is of a same conductivity as the first conductivity type (Can both be n-type or p-type [0008]).
Regarding Claim 11 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the first gate structure comprises one of an n-type work function metal or a p-type work function metal (lower work function metal [0037]), and the second gate structure comprises the other of the n-type work function metal or the p-type work function metal (upper work function metal [0037]).
Regarding Claim 12 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is located above a bottom dielectric isolation layer (DIL in annotated Fig. 8e) that is present on a semiconductor substrate (Although unlabeled by Chanemougame, this type of dielectric layer is common in nanosheet FETs to electrically isolate the FET(s) from the substrate, and creates continuity with layer 408, which serves the same purpose [0035]).
Regarding Claim 13 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the first field effect transistor is located in a first device region (492 [0037] and 8e), and the second field effect transistor is located in a second device region (493 [0037] and Fig. 8e), wherein the first device region is spaced apart from the second device region by a device separating dielectric material layer (418 [0037] and Fig. 8e).
Regarding Claim 14 – Chanemougame further discloses the semiconductor structure of Claim 1, wherein the first gate structure wraps around each first semiconductor channel material nanosheet of a plurality of first semiconductor channel material nanosheets ([0034] and Fig. 8e), and the second gate structure wraps around each second semiconductor channel material nanosheet of a plurality of second semiconductor channel material nanosheets ([0035] and Fig. 8e).
Regarding Claim 15 – Chanemougame further discloses the semiconductor structure of Claim 14, further comprising a first gate dielectric material layer separating the first gate structure from each first semiconductor channel material nanosheet of the plurality of first semiconductor channel material nanosheets, and a second gate dielectric material layer separating the second gate structure from each second semiconductor channel material nanosheet of the plurality of second semiconductor channel material nanosheets (For both upper and lower gate regions, a high-k dielectric is deposited between the channel and the work function metal as noted for the replacement gate process in [0037] and shown as HKD in annotated Fig. 8e).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al (US 20230017350 A1, hereinafter “Chanemougame”), in view of Smith et al (US 20210013111 A1, hereinafter “Smith”).
Regarding Claim 2 – Chanemougame discloses all the limitations of Claim 1.
Chanemougame fails to disclose the shunting material pillar is located along the first sidewall of both the first gate structure and the second gate structure, and along the second sidewall of both the first gate structure and the second gate structure.
However, Smith discloses the shunting material pillar is located along the first sidewall of both the first gate structure and the second gate structure, and along the second sidewall of both the first gate structure and the second gate structure (Smith [0081] and Fig. 19.
Smith discloses a similar nanosheet transistor structure to Chanemougame with a low resistance metal contacting the work function metal around the channels. Smith teaches placing low resistivity material such as cobalt, tungsten, or ruthenium on both sides of the gate structure for the benefit of lower gate resistance (Smith [0093]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chanemougame and Smith to place low resistivity shunt material on both sides of the gate structure for the benefit of lower resistance.
Regarding Claim 3 – Chanemougame discloses all the limitations of Claim 1.
Chanemougame fails to expressly disclose the shunting material pillar has a resistivity that is lower than a resistivity of both the first gate structure and the second gate structure.
However, Smith specifies several work function metal, both p-type (TiN) and n-type (TiAl, TiAlN, and TiAlC) (Smith [0084] and [0086]), all of which have higher resistivity than cobalt, tungsten, or ruthenium mentioned as shunting material (Chanemougame [0040]).
Material
Resistivity
Source
TiN
4750 nΩ m
Yun et al, “Electrical and Corrosion Properties of Titanium Aluminum Nitride Thin Films Prepared by Plasma-Enhanced Atomic Layer Deposition”, Journal of Materials Science & Technology, Volume 33, Issue 3, March 2017, Pages 295-299.
TiAl
Up to 420 nΩ m
https://www.periodic-table.org/titanium-electrical-resistivity/
TiAlN
28000 nΩ m
Yun et al, “Electrical and Corrosion Properties of Titanium Aluminum Nitride Thin Films Prepared by Plasma-Enhanced Atomic Layer Deposition”, Journal of Materials Science & Technology, Volume 33, Issue 3, March 2017, Pages 295-299.
TiAlC
10000+ nΩ m
Xiang et al, “Investigation of TiAlC by Atomic Layer Deposition as N Type Work Function Metal for FinFET”, ESC Journal of Solid State Science and Technology, Volume 4, Number 12, p 441.
Cobalt
62.4 nΩ m
https://www.periodic-table.org/cobalt-electrical-resistivity/
Tungsten
52.8 nΩ m
https://www.periodic-table.org/tungsten-electrical-resistivity/
Ruthenium
71 nΩ m
https://www.periodic-table.org/ruthenium-electrical-resistivity/
Smith discloses a similar nanosheet transistor structure to Chanemougame with a low resistance metal contacting the work function metal around the channels. Smith specifies some of the work function metals, making it possible to compare the properties of the materials and see the disclosed shunting pillar will inherently have lower resistivity than the work function metals contacting the gate dielectrics. See MPEP 2112(III).
Regarding Claim 4 – Chanemougame modified by Smith discloses all the limitations of Claim 3.
The combination of Chanemougame and Smith further discloses the shunting material pillar is composed of cobalt, tungsten, or ruthenium (Chanemougame [0041]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al (US 20230017350 A1, hereinafter “Chanemougame”), in view of Rachmady et al (US 20230395718 A1, hereinafter “Rachmady”).
Regarding Claim 16 – Chanemougame discloses all the limitations of Claim 1.
Chanemougame fails to disclose at least one other stacked field effect transistor device located laterally adjacent to first field effect transistor and the second field effect transistor, wherein the at least one other stacked field effect transistor device is devoid of a shunting material pillar.
However, Rachmady discloses at least one other stacked field effect transistor device located laterally adjacent to first field effect transistor and the second field effect transistor, wherein the at least one other stacked field effect transistor device is devoid of a shunting material pillar (using backside interconnections like 175a-c, Rachmady [0035] and Fig. 3A).
Like Chanemougame, Rachmady discloses stacked nanosheet transistors. Rachmady teaches the use of backside gate contacts for lower transistors in a stack for the benefit of direct gate contact by metal interconnects without routing a layer from the top of the transistor stack (Rachmady [0035] and Fig. 3A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Chanemougame and Rachmady to have at least one other stacked field effect transistor device located laterally adjacent to first field effect transistor and the second field effect transistor, devoid of a shunting material pillar, for the benefit of direct gate contact by metal interconnects without routing a layer from the top of the transistor stack.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898