DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Invention Group I in the reply filed on February 01, 2026 is acknowledged. Non-elected Invention , Claim 10 has been withdrawn from consideration. Claims 1-11 are pending.
Action on merits of the Elected Invention, claims 1-9 and 11 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-9 and 11 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites: “A dual-floating gates optoelectronic self-exciting synaptic memristor, comprising a bottom gate, a barrier layer coated on a surface of the bottom gate, a quantum dot layer coated on a surface of a middle portion of the barrier layer, two inverted L-shaped electron or hole tunneling layers coated on a surface of two end portions of the quantum dot layer respectively, two inverted L-shaped floating gate storage layers coated on the electron or hole tunneling layers respectively, two electron or hole blocking layers coated on the two floating gate storage layers respectively, an inverted L-shaped source electrode and an inverted L-shaped drain electrode coated on the two electron or hole blocking layers respectively, a photosensitive material layer coated on a surface of a middle portion of the quantum dot layer, and a top gate coated on the photosensitive material layer”.
The “dual-floating gates optoelectronic self-exciting synaptic memristor” operates in the same field effect principle as a transistor, which requires a conduction channel so that electrons or holes can be transferred to/from source and drain electrodes.
According to claim 1, the quantum dot layer (105) is completely isolated from the source electrode (103a) and the drain electrode (103b). Thus, no conduction channel existed or connecting between the source and drain.
Assuming an electric field can be asserted on the quantum dot layer (105) when a voltage is applied to the gates electrode, top (101) and bottom (102), there is no conduction channel for electrons or holes to traverse between source and drain electrodes; and the charges, if ever existed in the floating gate storage layers (106) can be transferred to the source and drain electrodes to be read or write.
Thus, the synaptic memristor as claimed cannot function.
Therefore, claim 1 and all dependent claims, fail to comply with the enablement requirement.
Since the claimed device failed to enable, an action on merits of the claims is excluded.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893