DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims are 1-8 and 11 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Anderson et al. US 20090020764 A1 (hereinafter Anderson).
Regarding claim 1, Anderson discloses a layer structure comprising:
a lower layer (Figure 17 shows element 10, a lower layer.);
an ion implantation layer in the lower layer (The elements 42, 16, and 14 are implantation regions formed in layer 10: elements 42 are regions of ion implantation forming source and drain regions [0077], elements 16 are halo implant regions [0091], and 14 is a lightly doped threshold voltage implantation region [0087].);
and a carbon-based material layer on the ion implantation layer (The carbon-based material layer is a graphene layer, element 20 in figure 17 [0086]),
wherein the ion implantation layer includes carbon (Referring to figure 17, the ion implant layer comprises elements 42, 16, and 14, which are all formed by doping the silicon carbide lower layer 10 [0089-0091, 0087].
Regarding claim 2, Anderson discloses the layer structure of claim 1,
wherein the ion implantation layer includes a trench (Figure 17, element 11 is a trench within the ion implant layer, 42, 16, and 14 [0084],
and the carbon-based material layer is in the trench (The graphene layer, figure 17 element 20, is formed within the trench, element 11 [0086]).
Regarding claim 4, Anderson discloses the layer structure of claim 2,
wherein the ion implantation layer has an ion implantation concentration gradient in a given direction of the ion implantation layer (Referring to figure 17, elements 42, 17, and 14 are all parts of the ion implementation layer [0089, 0091, 0087]. There is a gradient in ion implantation density as each of these areas has a different dopant density [0077, 0091, 0087].
Regarding claim 5, Anderson discloses the layer structure of claim 4,
wherein the ion implantation layer includes a plurality of layers
ii. that are sequentially stacked (Figure 17 shows that layers 42, 16, and 14, comprising the ion implantation layer, are sequentially stacked at different levels) and
have different ion implantation concentrations from each other (Each of these layers, has a different dopant density [0077, 0091, 0087].
Regarding claim 6, Anderson discloses the layer structure of claim 1, further comprising:
an upper layer on a portion of the lower layer around the ion implantation layer. (Element 80 of figure 21 is an upper layer on a portion of the lower layer, 10, around the implantation layer,14).
Regarding claim 7, Anderson discloses the layer structure of claim 6, further comprising:
a barrier layer between the lower layer and the upper layer around the ion implantation layer. (Element 80 of figure 21 is an upper layer on a portion of the lower layer, 10, around the implantation layer 14, and 60 is a barrier layer between upper layer 80 and lower layer, 10).
Regarding claim 11, Anderson discloses the layer structure of claim 6,
wherein the carbon-based material layer includes a graphene layer, a layered graphene layer, an amorphous carbon layer, or a nanocrystalline graphene layer (Layer 20 in figure 21, where the carbon-based material layer is composed of graphene [0086]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Kim et al. US 20170179234 A1 (hereinafter Kim).
Regarding claims 8-10, Anderson discloses the layer structure of claim 1.
Anderson does not disclose:
[claim 8] that the carbon-based material layer includes a heteromaterial and carbon;
[claim 9] that the heteromaterial includes nitrogen, boron, or both nitrogen and boron; and
[claim 10] that the carbon-based material layer is a carbon compound layer including the heteromaterial.
However, Kim discloses a carbon-based heteromaterial – heteroatom-doped graphene with nitrogen and/or boron included in the hexagonal crystal structure (Figures 11 and 12 show the placement of the nitrogen and/or boron atoms within the heteroatom-doped graphene crystal structure), which could be layered together with graphene ([0139] and [0146]), to produce a layer including heteromaterial and carbon.
It would have been obvious to a person of ordinary skill in the art before the effective filing data to replace the graphene layer of Anderson with the heteroatom-doped graphene incorporating nitrogen and/or boron atoms as disclosed by Kim in order to enhance and tune the electrical properties of the layer. For example, adding dopants to the graphene could create a bandgap, which is not characteristic of undoped graphene, while preserving the desirable electrical and physical characteristics of graphene (Kim [0005- 0006])
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 20150235959 A1 (hereinafter Lee) in view of Anderson.
Lee discloses an electronic device (In figure 10, the device comprises memory cell MC1 connected to a bit line BL1 [0153]) comprising:
a data storage element (Element MR1 of figure 10 is a magnetoresistive data storage element [0153].);
a transistor (In figure 10, TR1 is a switching element that may be a transistor [0157].) connected to a first side of the data storage element (TR1 is connected to a first side of MR1 in figure 10 [0153].); and
a conductive layer (Figure 10, BL1 is a bit line) connected to a second side of the data storage element [0155].
Lee lacks wherein the conductive layer is connected to a second side of the data storage element through the layer structure of claim 1.
Anderson discloses the layer structure of claim 1 (see rejection of claim 1 above).
It would have been obvious to a person having ordinary skill in the art before the filing data to add the layer structure of Anderson to the circuit of the memory device between the conductive layer (bit line) and the second side of the data storage element of the electronic device disclosed by Lee to act as an efficient access transistor between the memory cell and the bit line, to improve access speed and reduce power consumption (Anderson [0009-0011]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Thur. 7:00 am- 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818