DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2,7,9-12 and 21-27 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by SUZUKI et al. (US20210074711A1).
Regarding claim 1, Fig.35 of SUZUKI teaches a semiconductor device, comprising:
a stack structure that comprises alternating insulating layers 42 (para.0068) and word line layers 23 (para.0068);
a first channel structure LP (para.0071) extending through the stack structure;
a first top select gate (TSG) layer 24a (para.0176) over the stack structure;
a second TSG layer 24b (para.0176) over the first TSG layer 24a;
a second channel structure UP (para.0071) extending through the first and second TSG layers 24b, the second channel structure UP being positioned over and coupled to the first channel structure LP; and
a dummy channel structure LHR (para.0157) extending through the insulating layers 42 and the word line layers 23 of the stack structure.
Annotated Fig.35
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Regarding claim 2, Fig.35 of SUZUKI teaches the semiconductor device according to claim 1, further comprising: a first dielectric layer 45 (para.0126) positioned between the first TSG layer 24a (para.0176) and the second TSG layer 24b (para.0176).
Regarding claim 7, Fig.5 of SUZUKI teaches the semiconductor device according to claim 1, further comprising:
a second dielectric layer 45 (para.0126) positioned over the second TSC layer 24a (para.0176): and
a third dielectric layer 46 (para.0123) positioned over the second dielectric layer 45, wherein the second channel structure further extends through the second and third dielectric layers.
Regarding claim 9, Fig.5 of SUZUKI teaches the semiconductor device according to claim 2, further comprising: an array region (see annotated Fig.35) and a staircase region (see annotated Fig.35) adjacent to the array region, wherein: the first channel structure LP (para.0071) and the second channel structure UP (para.0071) are positioned in the array region, and the staircase region includes a plurality of stairs.
Regarding claim 10, Fig.31 of SUZUKI teaches the semiconductor device according to claim 9, wherein the plurality of stairs comprises a first stair formed in the first and second TSG layers 24a,24b (para.0176), the semiconductor device further comprising:
a TSG contact SC (para.0092) extending from the first TSG layer 24a (para.0176) and through the first dielectric layer 45 (para.0126) and the second TSG layer 24b (para.0176) at the first stair of the plurality of stairs.
Regarding claim 11, Fig.31 of SUZUKI teaches the semiconductor device according to claim 9, wherein the plurality of stairs comprises a first stair formed in the first TSG layer 24a (para.0176) and a second stair formed in the second TSG layer 24b (para.0176), the semiconductor device further comprising:
a first TSG contact SCa (para.0174) extending from the first TSG layer 24a (para.0176) at the first stair of the plurality of stairs; and
a second TSG contact SCb (para.0174) extending from the second TSG layer 24b (para.0176) at the second stair of the plurality of stairs.
Regarding claim 12, Fig.31 of SUZUKI teaches the semiconductor device according to claim 7. further comprising:
a fourth dielectric layer 47 (para.0123) formed over the third dielectric layer 46 (para.0123); and
a contact CV (para.0075) positioned over the second channel structure UP (para.0071) and extending through the fourth dielectric layer 47.
Regarding claim 21, Fig.31 of SUZUKI teaches the semiconductor device of claim 1, further comprising:
an array region (see annotated Fig.35), in which the first channel structure LP (para.0071) and the second channel structure UP (para.0071) are positioned; and
a staircase region (see annotated Fig.35) positioned adjacent to the array region, wherein the dummy channel structure LHR (para.0157) is positioned within the array region (see annotated Fig.35).
Regarding claim 22, Fig.31 of SUZUKI teaches the semiconductor device of claim 1, further comprising:
an array region (see annotated Fig.35), in which the first channel structure LP (para.0071) and the second channel structure UP (para.0071) are positioned: and
a staircase region (see annotated Fig.35) positioned adjacent to the array region, wherein the dummy channel structure LHR (para.0157) is positioned within the staircase region (see annotated Fig.35).
Regarding claim 23, Fig.31 of SUZUKI teaches the semiconductor device of claim 1, wherein the dummy channel structure LHR (para.0157) has a different structure from the first channel structure LP (para.0071).
Regarding claim 24, Fig.31 of SUZUKI teaches the semiconductor device of claim 1, wherein the dummy channel structure LHR (para.0157) includes a block layer 37 (para.0157).
Regarding claim 25, Fig.31 of SUZUKI teaches the semiconductor device of claim 1, wherein the dunny channel structure LHR (para.0157) includes a charge layer 31 (para.0157).
Regarding claim 26, Fig.31 of SUZUKI teaches the semiconductor device of claim 10, wherein the TSG contact SCb (para.0174) is in contact with the second TSG layer 24b (para.0135).
Regarding claim 27, Fig.31 of SUZUKI teaches the semiconductor device of claim 10, wherein a side portion of the first TSG layer 24a (para.0135) and a side portion of the second TSG layer 24b (para.0135) are aligned at the staircase region (see annotated Fig.35).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over SUZUKI et al. (US20210074711A1) in view of MATSUBAYASHI et al. (US20220271093A1).
Regarding claim 3, SUZUKI further teaches the semiconductor device according to claim 1, wherein the word line layers 23 (para.0068) comprise tungsten.
SUZUKI does not teach wherein the first and second TSG layers comprise polysilicon.
MATSUBAYASHI teaches, in Fig.6, para.0272, wherein the materials constituting the upper storage gate electrode TSG and the lower storage gate electrode BSG are, for example, p-type polycrystalline silicon and wherein the word line WL is, for example, a linear conductor. The word line WL includes, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. The word line WL includes, for example, tungsten (W) (para.0457).
In view of such teachings by MATSUBAYASHI, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzuki by using polysilicon for the first and second TSG layers for the purpose of using a well-known conductive material and also since Matsubayashi establishes that tungsten and polysilicon can be equivalently used as a conductive material for electrodes. Therefore, it also would have been obvious to substitute one art recognized equivalent material for another. (MPEP 2143.I.B/2144.06).
Claims 4-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over SUZUKI et al. (US20210074711A1) in view of Fukuzumi et al. (US20220199641A1).
Regarding claim 4, Figs.5 and 6 of SUZUKI teaches the semiconductor device according to claim 1, wherein the first channel structure LP (para.0071) further comprises:
a blocking layer 38 (para.0157) extending through the word line layers and the insulating layers and further into a substrate 21 (para.0066) on which the stack structure is positioned;
a charge storage layer 37 (para.0157) formed over the blocking layer 38;
a tunneling layer 36 (para.0157) formed over the charge storage layer 37;
a channel layer 31 (para.0157) formed over the tunneling layer 36;
an isolation layer 30 (para.0157) formed over the channel layer 31.
SUZUKI does not teach a top channel contact formed over the isolation layer and in contact with the channel layer.
Fukuzumi teaches, in Fig.1L, a top channel contact 122 (para.0041) formed over the isolation layer 112 (para.0031) and in contact with the channel layer 114 (para.0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the conductive material 122 of Fukuzumi because the channel material 130 is in electrical communication with the channel material 114 through the conductive material 122 (Fukuzumi, [para.0055]).
Regarding claim 5, The semiconductor device according to claim 4, wherein the second channel structure further comprises:
a gate dielectric layer 128 (para.0051) extending through the first and second TSG layers 145 (para.0069); and
a second channel layer 130 (para.0055) formed along the gate dielectric layer 128 and over the top channel contact 122 (para.0041), the second channel layer 130 being in contact with the top channel contact 122.
Regarding claim 6, Fig.5 of SUZUKI teaches the semiconductor device according to claim 5, further comprising: a separation structure SHE (para.0061) extending along a direction parallel to the substrate 21 (para.0066), and extending through the second TSG layer 24b (para.0176).
Regarding claim 8, Fig.5 of SUZUKI teaches the semiconductor device according to claim 6. wherein the separation structure SHE (para.0061) further extends through a first dielectric layer and the first TSG layer 24a (para.0176).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over SUZUKI et al. (US20210074711A1) in view of Fukuzumi et al. (US20220199641A1) and in further view of Billingsley et al. (US20220037350A1).
Regarding claim 13, Fig.5 of SUZUKI teaches the semiconductor device according to claim 4, further comprising:
a slit structure SLT (para.0077) extending through the word line layers 23 (para.0068) and the insulating layers 42 (para.0068) and further extending along a direction parallel to the substrate 21 (para.0066); and
SUZUKI does not teach a separation structure extending along the direction parallel to the substrate, extending through the second TSG layer, and positioned over the slit structure.
Fig.1L of Billingsley teaches a separation structure 165 (para.0078) extending along the direction parallel to the substrate 107 (para.0028), extending through the second TSG layer 150 (para.0055), and positioned over the slit structure 124 (para.0077).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include slots 124 and 165 of Billingsley in the teachings of SUZUKI in order to separate the microelectronic device structure 100 into sub-block structures 166 (Billingsley, [para.0077]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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