DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Applicants remarks, filed on 04/01/2026, with respect to the rejection(s) of claims 1 and 27 under 35 U.S.C. 102(a)(1)/(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of different interpretation of Suzuki.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, depends on claim 6. Currently claim 6 is cancelled and so it is unclear what the claim 8 depends on. For purposes of compact prosecution, the examiner interprets claim 8 to depend from claim 1. Appropriate correction is required to resolve the dependency issue.
Regarding claim 8, claim 8 recites the separation structure. However, no claim from which claim 8 depends recites a separation structure. Therefore, the separation structure lacks a proper antecedent basis. Further, as a separation structure has not been recited earlier, it is unclear to which structure this separation structure refers. Appropriate correction is required to clarify the language and resolve the antecedent issue. For purposes of compact prosecution, the examiner interprets the separation structure to be a separation structure.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, claim 9 is reciting an array region and a staircase region. It is unclear if this recitation is introducing a new array region and a staircase region. Appropriate correction is required to clarify the language and resolve the antecedent issue. For purposes of compact prosecution, the examiner interprets “an array region and a staircase region” as the array region and the staircase region which are already recited in claim 1.
Claims 10,11,26 and 27 are also rejected as they depend on claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2,7,9-12 and 23-28 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Suzuki et al. (US20210074711A1).
Regarding claim 1, Fig.31 of Suzuki teaches a semiconductor device, comprising:
a stack structure (para.0054) that comprises alternating insulating layers 42 (para.0117) and word line layers 23 (para.0068);
a first channel structure LP (para.0071) extending through the stack structure;
a first top select gate (TSG) layer 24 (para.0069, see annotated Fig.31) over the stack structure;
a second TSG layer 24 (para.0069, see annotated Fig.31) over the first TSG layer 24;
a second channel structure UP (para.0071) extending through the first and second TSG layers 24, the second channel structure being positioned over and coupled to the first channel structure LP;
a dummy channel structure LHR (para.0157) extending through the insulating layers 42 and the word line layers 23 of the stack structure;
an array region (see annotated Fig.31), in which the first channel structure LP and the second channel structure UP are positioned; and
a staircase region (see annotated Fig.31) positioned adjacent to the array region,
wherein the dummy channel structure LHR is positioned within the array region.
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Regarding claim 2, Suzuki further teaches the semiconductor device according to claim 1, further comprising: a first dielectric layer 45 (para.0126) positioned between the first TSG layer 24 (para.0069, see annotated Fig.31) and the second TSG layer 24 (para.0069, see annotated Fig.31).
Regarding claim 7, Suzuki further teaches the semiconductor device according to claim 1, further comprising:
a second dielectric layer 45 (para.0126) positioned over the second TSG layer 24 (para.0069, see annotated Fig.31); and
a third dielectric layer 46 (para.0123) positioned over the second dielectric layer 45, wherein
the second channel structure LP (para.0071) further extends through the second and third dielectric layers 45,46.
Regarding claim 9, Suzuki further teaches the semiconductor device according to claim 2, further comprising:
an array region (see annotated Fig.31) and a staircase region (see annotated Fig.31) adjacent to the array region, wherein:
the first channel structure LP (para.0071) and the second channel structure UP (para.0071) are positioned in the array region, and
the staircase region includes a plurality of stairs.
Regarding claim 10, Suzuki further teaches the semiconductor device according to claim 9, wherein the plurality of stairs comprises a first stair formed in the first and second TSG layers 24 (para.0069, see annotated Fig.31), the semiconductor device further comprising:
a TSG contact SC (para.0092) extending from the first TSG layer and through the first dielectric layer 45 (para.0126) and the second TSG layer 24 (para.0069, see annotated Fig.31) at the first stair of the plurality of stairs.
Regarding claim 11, Fig.35 of Suzuki teaches the semiconductor device according to claim 9, wherein the plurality of stairs comprises a first stair formed in the first TSG layer 24a (para.0176) and a second stair formed in the second TSG layer 24b (para.0176), the semiconductor device further comprising:
a first TSG contact SCa (para.0174) extending from the first TSG layer 24a at the first stair of the plurality of stairs; and
a second TSG contact SCb (para.0174) extending from the second TSG layer 24b at the second stair of the plurality of stairs.
Regarding claim 12, Suzuki further teaches the semiconductor device according to claim 7, further comprising:
a fourth dielectric layer 47 (para.0123) formed over the third dielectric layer 46 (para.0123); and
a contact CV (para.0075) positioned over the second channel structure UP (para.0071) and extending through the fourth dielectric layer 47.
Regarding claim 23, Fig.31 of Suzuki further teaches the semiconductor device of claim 1, wherein the dummy channel structure LHR (para.0157) has a different structure from the first channel structure LP (para.0071).
Regarding claim 24, Fig.31 of Suzuki further teaches the semiconductor device of claim 1, wherein the dummy channel structure LHR (para.0157) includes a block layer 37 (para.0157).
Regarding claim 25, Suzuki further teaches the semiconductor device of claim 1, wherein the dummy channel structure LHR (para.0157) includes a charge layer 31 (para.0157).
Regarding claim 26, Suzuki further teaches the semiconductor device of claim 10, wherein the TSG contact SCb (para.0174) is in contact with the second TSG layer 24 (para.0069, see annotated Fig.31).
Regarding claim 27, Suzuki further teaches the semiconductor device of claim 10, wherein a side portion of the first TSG layer 24 (para.0069, see annotated Fig.31) and a side portion of the second TSG layer 24 (para.0069, see annotated Fig.31) are aligned at the staircase region (see annotated Fig.31).
Regarding claim 28, Fig.31 of Suzuki teaches a semiconductor device, comprising:
a stack structure (para.0054) that comprises alternating insulating layers 42 (para.0117) and word line layers 23 (para.0068); a first channel structure LP (para.0071) extending through the stack structure;
a first top select gate (TSG) layer 24 (para.0069, see annotated Fig.31) over the stack structure;
a second TSG layer 24 (para.0069, see annotated Fig.31) over the first TSG layer 24;
a second channel structure UP (para.0071) extending through the first and second TSG layers 24, the second channel structure UP being positioned over and coupled to the first channel structure LP;
a dummy channel structure LHR (para.0157) extending through the insulating layers 42 and the word line layers 23 of the stack structure;
a first dielectric layer 45 (para.0126) positioned between the first TSG layer and the second TSG layer; and
an array region (see annotated Fig.31) and a staircase region (see annotated Fig.31) adjacent to the array region,
wherein the first channel structure LP and the second channel structure UP are positioned in the array region,
the staircase region includes a plurality of stairs, the plurality of stairs comprising a first stair (see annotated Fig.31) formed in the first and second TSG layers 24,
the semiconductor device further comprises a TSG contact SC (para.0092) extending from the first TSG layer 24 and through the first dielectric layer 45 and the second TSG layer 24 at the first stair of the plurality of stairs, and a side portion of the first TSG layer 24 (para.0069, see annotated Fig.31) and a side portion of the second TSG layer 24 (para.0069, see annotated Fig.31) are aligned at the staircase region (see annotated Fig.31).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US20210074711A1) in view of MATSUBAYASHI et al. (US20220271093A1).
Regarding claim 3, Suzuki further teaches the semiconductor device according to claim 1, wherein the word line layers 23 (para.0068) comprise tungsten.
Suzuki does not teach wherein the first and second TSG layers comprise polysilicon.
Fig.6 of MATSUBAYASHI teaches a memory device that includes materials constituting the upper storage gate electrode TSG and the lower storage gate electrode BSG are, for example, p-type polycrystalline silicon and wherein word line WL is, for example, a linear conductor. The word line WL includes, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. The word line WL includes, for example, tungsten (W) (para. 0272, 0457).
In view of such teachings by MATSUBAYASHI, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzuki by using polysilicon for the first and second TSG layers for the purpose of using a well-known conductive material and also since Matsubayashi establishes that tungsten and polysilicon can be equivalently used as a conductive material for electrodes. Therefore, it also would have been obvious to substitute one art recognized equivalent material for another. (MPEP 2143.I.B/2144.06).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US20210074711A1) in view of Fukuzumi et al. (US20220199641A1).
Regarding claim 4, Figs. 5 and 6 of SUZUKI teaches the semiconductor device according to claim 1, wherein the first channel structure LP (para.0071) further comprises:
a blocking layer 38 (para.0080) extending through the word line layers 23 (para.0068) and the insulating layers 42 (para.0117) and further into a substrate on which the stack structure (para.0054) is positioned;
a charge storage layer 37 (para.0082) formed over the blocking layer 38;
a tunneling layer 36 (para.0080) formed over the charge storage layer 37; a channel layer 31 (para.0072) formed over the tunneling layer 36;
an isolation layer 30 (para.0072) formed over the channel layer 31.
SUZUKI does not teach a top channel contact formed over the isolation layer and in contact with the channel layer.
Fig.1L of Fukuzumi teaches a top channel contact 122 (para.0041) formed over the isolation layer 112 (para.0031) and in contact with the channel layer 114 (para.0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the conductive material 122 of Fukuzumi in the teachings of SUZUKI in order to provide electrical communication between the channel material 130 and the channel material 114 (Fukuzumi, [para.0055]).
Regarding claim 5, the combination of SUZUKI and Fukuzumi teaches the semiconductor device according to claim 4, wherein the second channel structure 135 (para.0061) further comprises:
a gate dielectric layer 128 (para.0051) extending through the first and second TSG layers 145 (para.0069); and
a second channel layer 130 (para.0055) formed along the gate dielectric layer 128 and over the top channel contact 122 (para.0041), the second channel layer 130 being in contact with the top channel contact 122.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US20210074711A1) in view of Shin et al. (US11552101B2).
Regarding claim 8, Suzuki does not teach wherein the separation structure further extends through a first dielectric layer and the first TSG layer.
Fig.11D of Shin teaches a semiconductor device that includes electrode patterns surrounding second channel structures and separated from each other by first slits and second slits; wherein the separation structure 361A (col.18, line 62) further extends through a first dielectric layer 121/BT (col.16, lines 15-16) and the first TSG layer 355 (col.19, lines 25-26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the separation insulating layer 361A of Shin in the teachings of Suzuki in order to separate drain select lines included in each of the memory blocks from each other (Shin, [col.18, lines 66-67]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US20210074711A1) in view of Lee et al. (US9859293B2).
Regarding claim 13, Suzuki teaches the semiconductor device according to claim 4, further comprising:
a slit structure SLT (para.0055) extending through the word line layers 23 (para.0068) and the insulating layers 42 (para.0117) and further extending along a direction parallel to the substrate 20 (para.0066).
Suzuki does not teach a separation structure extending along the direction parallel to the substrate, extending through the second TSG layer, and positioned over the slit structure.
Fig.8B of Lee teaches a semiconductor device that includes cell stack structure CML and an upper stack structure UML stacked on the cell stack structure CML; and wherein slits SI are isolating the cell stack structures CML from each other (col.6, lines 49-50) and the first upper stack structure UML1 and the second upper stack structure UML2 may have sidewalls defined by second upper slits USI2 (col.6, lines 54-57); wherein a separation structure USI2 (col.6, lines 56-57) extending along the direction parallel to the substrate, extending through the second TSG layer CPn+1 (col.7, lines 10-11), and positioned over the slit structure SI (col.6, line 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the upper slits USI2 of Lee in the teachings of Suzuki in order for the upper slits USI2 to isolate the first and second upper stack structures UML1 and UML2 and for the slits SI to isolate the cell stack structures from each other (col.11, lines 52-54, col.6, lines 49-50).
Claims 29 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US20210074711A1) in view of Lu et al. (US20170352678A1).
Regarding claim 29, Suzuki further teaches the semiconductor device of claim 1, further comprising:
a substrate 20 (para.0066) on which the stack structure (para.0054) is positioned.
Suzuki does not teach a separation structure extending along a direction parallel to the substrate and extending through the second TSG layer, wherein the separation structure does not run through the first TSG layer.
Fig.11 of Lu teaches a memory device that includes drain-select-level shallow trench isolation structures 72 that are formed through a subset of layers in an upper portion of the second-tier alternating stack (232, 242) (para.0082); wherein a separation structure 72 (para.0101) extending along a direction parallel to the substrate 9 (para.0102) and extending through the second TSG layer (see annotated Fig.11), wherein the separation structure 72 does not run through the first TSG layer (see annotated Fig.11).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the isolation structures of LU in the teachings of Suzuki in order to divide a subset of layers in an upper portion of the second-tier alternating stack (232, 242) within each sub-block or within each block (LU, [para.0101]).
Regarding claim 30, Suzuki further teaches the semiconductor device of claim 28, further comprising:
a substrate 20 (para.0066) on which the stack structure (para.0054) is positioned.
Suzuki does not teach a separation structure extending along a direction parallel to the substrate and extending through the second TSG layer, wherein the separation structure does not run through the first TSG layer.
Fig.11 of Lu teaches a memory device that includes drain-select-level shallow trench isolation structures 72 that are formed through a subset of layers in an upper portion of the second-tier alternating stack (232, 242) (para.0082); wherein a separation structure 72 (para.0101) extending along a direction parallel to the substrate 9 (para.0102) and extending through the second TSG layer (see annotated Fig.11), wherein the separation structure 72 does not run through the first TSG layer (see annotated Fig.11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the isolation structures of LU in the teachings of Suzuki in order to divide a subset of layers in an upper portion of the second-tier alternating stack (232, 242) within each sub-block or within each block (LU, [para.0101]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights