DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (encompassing claims 1-9) in the reply filed on 12/18/25 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/23/22. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liang et al. (U.S. 2020/0204175 A1; “Liang”).
Regarding claim 1, Liang discloses a CMOS complementary metal-oxide-semiconductor (CMOS) apparatus comprising:
An interconnect layer (388, Fig. 3A), which has a front side and a backside opposite the front side ([0057]);
An n-doped field effect transistor (nFET) (331, Fig. 3A) ([0003]) disposed at the backside of the interconnect layer, wherein the nFET comprises an nFET drain structure (374, Fig. 3A), an nFET source structure (372, Fig. 3A), and an nFET channel structure (382, Fig. 3A) that is connected between the nFET drain structure and the nFET source structure, wherein the nFET has a front side surface adjacent to the interconnect layer and a backside surface opposite to the interconnect layer ([0047]);
A p-doped field effect transistor (pFET) (333, Fig. 3A) ([0003]) disposed at the backside of the interconnect layer adjacent to the nFET, wherein the pFET comprises a pFET drain structure (374, Fig. 3A), a pFET source structure (376, Fig. 3A), and a pFET channel structure (384, Fig. 3A) that is connected between the pFET drain structure and the pFET source structure, wherein the pFET has a front side surface adjacent to the interconnect layer and a backside surface opposite to the interconnect layer ([0048]); and
A backside drain contact (394a, 396a, 397, Fig. 3), disposed at the backside surface of the nFET and the pFET and electrically connected to the nFET drain structure and to the pFET drain structure ([0052], [0055]).
Regarding claim 2, Liang discloses the backside drain contact (394a, 396a, 397, Fig. 3) comprises: a metal pillar (394a, Fig. 3) disposed between, and directly contacting, adjacent facing surfaces of the nFET and pFET drain structures (374, Fig. 3).
Regarding claim 7, Liang discloses shallow trench isolation material at either side of the backside drain contact.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. 2020/0204175 A1; “Liang”) as applied to claim 1 above, and further in view of Liaw (U.S. 2022/0328641 A1).
Regarding claim 8, Liang discloses a gate stack including a gate structure (356, 358, Fig. 3A) but does not disclose the gate structure is a gate-all-around structure ([0047]-[0048]). However, Liaw discloses using a gate-all-around gate structure within a gate-all-around device ([0002], [0031]). This has the advantage of forming transistor devices with increased power efficiency and decreased size. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Liang with the gate structure being a gate-all-around gate structure, as taught by Liaw, so as to improve power efficiency and decrease apparatus size.
Allowable Subject Matter
Claims 3-6 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 1/6/26
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