DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 12/18/2025 that has been entered, wherein claims 1, 3-5, 9-10, 12-23 are pending, claims 2, 6-8 and 11 are canceled and claims 17-20 are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2023/0395477 A1) and Yasunaga et al. (US 2003/0155634 A1), both of record.
Regarding claim 1, Lee teaches an electronic device(Fig. 2h), comprising:
a multilevel metallization structure(120, ¶0020) having multiple levels of conductive metal traces(horizontal electrical interconnect of 122, ¶0020) and vias(124, ¶0020) and polyimide insulator material(123, ¶0020), including a first level along a first side(128, ¶0020) and a final level along a second side(126, ¶0020), the first level including conductive metal leads(exposed surface of 122 along 128, exposed surface of 124, ¶0020, ¶0033) with exposed surfaces along the first side(128, ¶0020), and the final level including conductive metal pads(exposed surface of 122 along 126, ¶0020) with exposed surfaces along the second side(126, ¶0020);
a semiconductor die(130a, ¶0021) having conductive features, the semiconductor die(130a, ¶0021) flip chip attached to the second side(126, ¶0020) of the multilevel metallization structure(120, ¶0020) with the conductive features(112, ¶0018, ¶0021) connected to respective one of the conductive metal pads(exposed surface of 122 along 126, ¶0020); and
a package structure(136, ¶0022) that encloses the semiconductor die(130a, ¶0021), wherein:
the electronic device has a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side;
the first side extends in a first plane of orthogonal first and second directions;
the second side extends in a second plane of the first and second directions and is spaced apart from the first side along a third direction that is orthogonal to the first and second directions;
the third, fourth, fifth, and sixth sides extend from the first side to the second side along the third direction; and
the conductive metal leads(exposed surface of 122 along 128, exposed surface of 124, ¶0020, ¶0033) have second surfaces exposed along respective ones of the third, fourth, fifth, and sixth sides(please see examiner annotated Fig. 5, ¶0033).
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Lee is not relied on to teach the conductive metal leads(exposed surface of 122 along 128, exposed surface of 124, ¶0020, ¶0033) include indented undercut features along the first side(128, ¶0020).
Yasunaga teaches an electronic device(Fig. 11) wherein the conductive metal leads(10, ¶0006) include indented undercut(12, ¶0006) features along the first side(14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee, so that the conductive metal leads include indented undercut features along the first side, as taught by Yasunaga, in order to facilitate bonding of the encapsulating insulating material layer to the lead(¶0007) while diminishing the tendency of the lead from separating from the encapsulating insulating material layer(¶0006).
Regarding claim 3, Lee teaches the electronic device of claim 1, wherein the conductive metal leads(exposed surface of 122 along 128, exposed surface of 124, ¶0020, ¶0033) and the conductive metal pads(exposed surface of 122 along 126, ¶0020) include copper(¶0020).
Regarding claim 4, Lee teaches the electronic device of claim 2.
The embodiment of fig. 2h of Lee is not relied on to teach the electronic device has a quad flat no-lead shape.
The embodiment of fig. 7 of Leah teaches an electronic device(Fig. 7) the electronic device(300) has a quad flat no-lead shape(320, ¶0040). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of fig. 2h of Lee, so that the electronic device has a quad flat no-lead shape, as taught by the embodiment of fig. 7 of Lee, so that the electronic device can be manufactured using less expensive components and a streamlined manufacturing process resulting in an electronic device that is less likely to fail and less expensive to manufacture resulting in a lower cost for consumers(¶0040).
Regarding claim 5, Lee teaches the electronic device of claim 2, wherein:
the conductive features(112, ¶0018, ¶0021) are connected to respective ones of a first set of the conductive metal pads(exposed surface of 122 along 126, ¶0020); and
the electronic device further comprises an additional die(130b, ¶0021) or a passive component connected to respective ones of a second set of the conductive metal pads(exposed surface of 122 along 126, ¶0020).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2023/0395477 A1) and Yasunaga et al. (US 2003/0155634 A1) as applied to claim 1 above, and further in view of Chen et al. (US 2017/0005023 A1) all of record.
Regarding claim 9, Lee, in view of Yasunaga teaches the electronic device of claim 1.
Lee and Yasunaga are not relied on to teach the conductive metal leads(exposed surface of 122 along 128, exposed surface of 124, ¶0020, ¶0033) include a solderable finish on the exposed surfaces along the first side(128, ¶0020).
Chen teaches an electronic device(Fig. 2H) wherein the conductive metal leads(211, ¶0032) include a solderable finish(¶0032) on the exposed surfaces along the first side(21a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee, so that the conductive metal leads include a solderable finish on the exposed surfaces along the first side, as taught by Lee, in order to bond electronic elements to the first side of the multilevel metallization structure(¶0032).
Allowable Subject Matter
Claims 10, 12-16 and 21-23 are allowed. Please see the office action dated 5/12/2025 for reasons for allowance.
Response to Arguments
Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant’s argue the office action on page 8 indicates that an ordinary artisan would have been motivated to modify Lee to incorporate the teachings of Yasunaga in order to facilitate bonding of the encapsulating material to the lead while diminishing the tendency of the lead from separating from the encapsulating material. Applicant respectfully disagrees. In Lee, as shown in Fig. 2h, the encapsulant 136 does not cover the conductive layers 122 along the bottom side of the interconnect substrate. That is, the conductive layers 122 on the bottom side of the interconnect substrate are not in contact with the encapsulant 136. There is no bonding of encapsulating material to the lead, because the encapsulating material does not contact the lead on the bottom surface of the substrate. Thus, an ordinary artisan would not have been motivated to modify Lee to incorporate the teachings of Yasunaga, because such modification is unnecessary and would make the structure of the interconnect substrate of Lee more complicated without any practical benefits. The other cited reference does not remedy the deficiency of Lee and Yasunaga. Claim 1 as amended is patentable over the cited references.
The examiner respectfully submits that the conductive layers 122 of Lee are encapsulated in insulating material layer 123. A person of ordinary skill in the art would be motivated to facilitate bonding of the encapsulating insulating material 123 to the conductive lead layers 122 and prevent the conductive lead layers 122 from separating from the encapsulating insulating material 123. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee, so that the conductive metal leads include indented undercut features along the first side, as taught by Yasunaga, in order to facilitate bonding of the encapsulating insulating material layer to the lead(¶0007) while diminishing the tendency of the lead from separating from the encapsulating insulating material layer(¶0006).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892