Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section titled “Rejections under 35 U.S.C. 102,” filed 01/22/2026, with respect to the rejection(s) of claims 1-20 under 35 U.S.C 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Huang et al. (US20220199624A1, hereinafter Huang).
Regarding claim 1, Huang discloses a semiconductor structure comprising:
a first memory array (Fig. 3A frontside bit cell 10); and
a second memory array directly connected to the first memory array by nanosheet stacks (Fig. 3A, par. 30 backside bit cell 20 connected to frontside bit cell through transistor stack structure 30 “has a GAA transistor architecture with a plurality of stacked channel regions 105”);
and backside contacts (Fig. 3A backside interconnect 182), wherein a gate contact is horizontally between source/drain (S/D) contacts in the first memory array and S/D contacts in the second memory array (Fig. 3A gate electrode 110 is horizontally between source/drain regions 106 in both frontside bit cell 10 and backside bit cell 20).
See below for full claims mapping on the remaining claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-12, and 14-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Huang (US20220199624A1).
Regarding claim 1, Huang discloses a semiconductor structure comprising:
a first memory array (Fig. 3A frontside bit cell 10); and
a second memory array directly connected to the first memory array by nanosheet stacks (Fig. 3A, par. 30 backside bit cell 20 connected to frontside bit cell through transistor stack structure 30 “has a GAA transistor architecture with a plurality of stacked channel regions 105”);
and backside contacts (Fig. 3A backside interconnect 182), wherein a gate contact is horizontally between source/drain (S/D) contacts in the first memory array and S/D contacts in the second memory array (Fig. 3A gate electrode 110 is horizontally between source/drain regions 106 in both frontside bit cell 10 and backside bit cell 20).
Regarding claim 2, Huang discloses the semiconductor structure of claim 1,
wherein the first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer (Par. 28 teaches that “[f]abrication of double-sided, or “double-layered” stacked memory may leverage monolithic stacked transistor structures that include GAA, stacked RoW channels, which are also suitable for advanced logic (CMOS) circuitry” and “[s]tacked transistor structures suitable for advanced CMOS may be further leveraged in double-sided DRAM architectures through the application of backside transistor interconnect technology”).
Regarding claim 4, Huang discloses The semiconductor structure of claim 1,
wherein the backside contacts are through silicon vias (TSV) (Figs. 1, 3A see substrate region 103 below lower transistor 102 wherein backside interconnect 182 is disposed and so the backside interconnect is also a TSV).
Regarding claim 5, Huang discloses the semiconductor structure of claim 1,
wherein the nanosheet stacks separate the first memory array from the second memory array (Fig. 3A frontside bit cell 10 and backside bit cell 20 are separated from each other by transistor stack structure 30).
Regarding claim 6, Huang discloses the semiconductor structure of claim 1,
wherein the nanosheet stacks are separated from each other by source/drain (S/D) regions (Fig. 3A frontside bit cell 10 and backside bit cell 20 are separated from each other by source/drain region 106).
Regarding claim 7, Huang discloses the semiconductor structure of claim 1,
wherein the S/D contacts in the first memory array are vertically offset from the S/D contacts in the second memory array (Fig. 3A frontside source/drain contact 161 upper transistor 101 are vertically offset from backside source/drain contacts 108 in lower transistor 101).
Regarding claim 8, Huang discloses the semiconductor structure of claim 7,
wherein the S/D contacts in the first memory array and the S/D contacts in the second memory array are vertically offset from the nanosheet stacks (Fig. 3A frontside source/drain contact 161 and backside contacts 108 are vertically offset from channel regions 105).
Regarding claim 9, Huang discloses the semiconductor structure of claim 1,
wherein top surfaces of the nanosheet stacks directly contact gate contacts extending into the first memory array (Fig. 3A top surface of topmost channel region 105 contacts gate electrode 110 which extends into frontside bit cell 10) and bottom surfaces of the nanosheet stacks directly contact oxide layers placed adjacent the second memory array (Fig. 3A bottom surface of bottommost channel region 105 directly contacts gate dielectrics 217 which are placed adjacent to the backside bit cell 20).
Regarding claim 10, Huang discloses a semiconductor structure comprising:
a first memory array (Fig. 3A frontside bit cell 10); and
a second memory array integrated with the first memory array by at least a plurality of nanosheet stacks to define a single complementary metal oxide semiconductor (CMOS) chip (Fig. 3A, par. 30 backside bit cell 20 connected to frontside bit cell through transistor stack structure 30 “has a GAA transistor architecture with a plurality of stacked channel regions 105” and par. 28 teaches that Par. 28 teaches that “[f]abrication of double-sided, or “double-layered” stacked memory may leverage monolithic stacked transistor structures that include GAA, stacked RoW channels, which are also suitable for advanced logic (CMOS) circuitry” and “[s]tacked transistor structures suitable for advanced CMOS may be further leveraged in double-sided DRAM architectures through the application of backside transistor interconnect technology”), wherein a gate contact is horizontally between source/drain (S/D) contacts in the first memory array and S/D contacts in the second memory array (Fig. 3A gate electrode 110 is horizontally between source/drain regions 106 in both frontside bit cell 10 and backside bit cell 20).
Regarding claim 12, Huang discloses the semiconductor structure of claim 10,
wherein the first and second memory arrays are further integrated by a plurality of backside contacts (Fig. 3A backside interconnect 182 and backside source/drain contacts 108).
Regarding claim 14, Huang discloses the semiconductor structure of claim 10,
wherein the nanosheet stacks separate the first memory array from the second memory array (Fig. 3A frontside bit cell 10 and backside bit cell 20 are separated from each other by transistor stack structure 30).
Regarding claim 15, Huang discloses the semiconductor structure of claim 10,
wherein the nanosheet stacks are separated from each other by source/drain (S/D) regions (Fig. 3A frontside bit cell 10 and backside bit cell 20 are separated from each other by source/drain region 106).
Regarding claim 16, Huang discloses the semiconductor structure of claim 10,
wherein the S/D contacts in the first memory array are vertically offset from the S/D contacts in the second (Fig. 3A frontside source/drain contact 161 upper transistor 101 are vertically offset from backside source/drain contacts 108 in lower transistor 101).
Regarding claim 17, Huang discloses the semiconductor structure of claim 16,
wherein the S/D contacts in the first memory array and the S/D contacts in the second memory array are vertically offset from the nanosheet stacks (Fig. 3A frontside source/drain contact 161 and backside contacts 108 are vertically offset from channel regions 105).
Regarding claim 18, Huang discloses the semiconductor structure of claim 10,
wherein top surfaces of the nanosheet stacks directly contact gate contacts extending into the first memory array (Fig. 3A top surface of topmost channel region 105 contacts gate electrode 110 which extends into frontside bit cell 10) and bottom surfaces of the nanosheet stacks directly contact oxide layers placed adjacent the second memory (Fig. 3A bottom surface of bottommost channel region 105 directly contacts gate dielectrics 217 which are placed adjacent to the backside bit cell 20).
Regarding claim 19, Huang discloses a method comprising:
forming a first set of source/drain (S/D) contacts (Fig. 3A source/drain regions 106 within upper transistor 101) within a silicon on insulator (SOI) layer of a wafer (Par. 35 “channel regions 105 were formed from a semiconductor layer of an semiconductor-on-insulator (SOI) substrate” and so it is formed within an SOI layer of a wafer);
forming nanosheet stacks over portions of the SOI layer (Fig. 3A channel regions 105 and par. 35 teaches that “channel regions 105 were formed from a semiconductor layer of an semiconductor-on-insulator (SOI) substrate”);
constructing a first memory array (Fig. 3A frontside bit cell 10);
flipping the wafer;
removing the portions of the SOI layer (Fig. 6 steps 610-630 comprise flipping wafer and then subsequently removing backside portions of the substrate to form backside contacts);
constructing a second memory array (Fig. 3A backside bit cell 20); and
re-flipping the wafer so that the second memory array is integrated with the first memory array by at least the nanosheet stacks to define a single complementary metal oxide semiconductor (CMOS) chip (Fig. 3A shows a completed device with two memory arrays in frontstide bit 10 and backside bit 20 in an upright configuration and par. 28 teaches that “[f]abrication of double-sided, or “double-layered” stacked memory may leverage monolithic stacked transistor structures that include GAA, stacked RoW channels, which are also suitable for advanced logic (CMOS) circuitry” and “[s]tacked transistor structures suitable for advanced CMOS may be further leveraged in double-sided DRAM architectures through the application of backside transistor interconnect technology”).
Regarding claim 20, Huang discloses the method of claim 19,
wherein the nanosheet stacks separate the first memory array from the second memory array (Fig. 3A frontside bit cell 10 and backside bit cell 20 are separated from each other by transistor stack structure 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wang et al. (US20190386062A1, hereinafter Wang).
Regarding claim 3, Huang teaches the semiconductor structure of claim 1.
Huang does not appear to teach
wherein the first memory array is a first type of memory device and the second memory array is a second type of memory device different than the first type of memory device.
Wang teaches
wherein the first memory array is a first type of memory device and the second memory array is a second type of memory device different than the first type of memory device (Wang fig. 3C SHE-MRAM 342 is a different type of memory device than STT-MRAM 360).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Huang with the teachings of Wang because as both Huang and Wang teach suitable configurations for use in a DRAM device, it would have been obvious to substitute Huang’s configuration where the first and second memory arrays are the same type of memory devices with Wang’s configuration where the first and second memory arrays are SHE-MRAM and STT-MRAM to achieve the predictable result of forming a memory device wherein the first memory array is a first type of memory device and the second memory array is a second type of memory device different than the first type of memory device.
Regarding claim 13, Huang teaches the semiconductor structure of claim 10.
Huang does not appear to teach
wherein the first memory array is a first type of memory device and the second memory array is a second type of memory device different than the first type of memory device.
Wang teaches
wherein the first memory array is a first type of memory device and the second memory array is a second type of memory device different than the first type of memory device (Wang fig. 3C SHE-MRAM 342 is a different type of memory device than STT-MRAM 360).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Huang with the teachings of Wang because as both Huang and Wang teach suitable configurations for use in a DRAM device, it would have been obvious to substitute Huang’s configuration where the first and second memory arrays are the same type of memory devices with Wang’s configuration where the first and second memory arrays are SHE-MRAM and STT-MRAM to achieve the predictable result of forming a memory device wherein the first memory array is a first type of memory device and the second memory array is a second type of memory device different than the first type of memory device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812