DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
This is in response to applicant’s amendment/response filed on 07/10/2025, which have been entered and made of record. Claims 11-17 and 20-21 have been amended. Claims 22-31 have been added. Claims 11-31 are pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 and 17, recites “each cacheline-sized microvertex displacement block being sized to fit into a respective single cache line of the cache memory”. It is not clear what should be defined by “each cacheline-sized microvertex displacement block being sized to fit into a respective single cache line…” It is unclear how the displacement block being sized to fit into single cache line. Should the block be truncated or added some data to fit the single cache line? Should the block be exactly the same size in byte or be smaller/loosely fit the single cache line? Since “plural cache lines each having a cacheline size”, it is unclear whether each cache line has the same size of different size. If each cache line is different in size, it is unclear how the (compressed) microvertex displacement block being sized to fit into the respective cache line. it is unclear what amount of a block (microvertices of a sub-triangle or sub-triangles) are fitting into a single cacheline-sized. It is also unclear what “microvertex displacements” of a block to predict (a microvertex height, a microvertex coordinates, its normal, its UV coordinates or something else.) For claim 11, it is also unclear whether “each cacheline-sized microvertex displacement block” is one of the compressed cacheline-sized microvertex displacement blocks.
All dependent claims are also rejected based on their dependency of the defected parent claims.
Notes: Specification in pars. [0070-0071], discloses a displacement value is stored for each microvertex of the micromesh. These displacement values are stored in displacement blocks such as shown in FIG. 6. The displacement blocks in which the displacement values are stored are of a fixed size… For example, in one embodiment, all displacement values for all vertices of a sub triangle are configured to fit within a single cache line (e.g., in one example, a full cacheline is 128 bytes and a half cacheline is 64 bytes)… [0071], no compression is needed in order to fit displacement values for lower tessellation levels into a single cacheline. As FIG. 6 shows, lower tessellation levels are less compressed and their displacement blocks may contain the full precision displacement value for each vertex.
The closest prior art:
Lee (US 20080256300), at least in pars. [0040-0044, 0048-0049], teaches the cache configuration logic 106 may reconfigure the cache 126 by modifying the cache line size and the number of cache lines of the cache… cache configuration logic to establish a number of cache lines based on the cache line size and a total size of the vertex cache.
Arteru (Storing vertex data: To interleave or not to interleave?) teaches When it comes to storing vertex data, there’s basically two different schools of thought. One says interleave the attributes, that is, store “fat” vertices which contain position, normal, UV coordinates and so on together. I’ll refer to this as interleaved storage, as it interleaves all vertex attributes in memory. The other school says all attributes should remain separate, so a vertex consists of multiple streams. Each stream stores one attribute only with tight packing… Reading the position from vertices storing the various attributes interleaved. Only four vertices fit into a single cache line, and more than half of the cache line is discarded.
PNG
media_image1.png
615
1046
media_image1.png
Greyscale
PNG
media_image2.png
649
1048
media_image2.png
Greyscale
Luebke (US 20180096516) teaches during re-projection of dynamic objects, the hit point position may be found by looking up the new locations of the hit point's triangle vertices (which may be computed already to generate the new acceleration structure this frame) and interpolating using the barycentric coordinates. This may incur extra memory traffic to look up the vertices, but cache locality may be efficient if nearby hit points are computed at the same time (using a space-filling curve) [0110].
Riguer (US 20220101483) teaches in par. [0051] each node is associated with metadata indicating its relationship with the acceleration data structure 500. The metadata is maintained as an attribute of the node. Attributes of primitive include position information, color information, and texture information for each of its vertices, and the metadata indicating its level in the hierarchy of the acceleration data structure 500.
Laine (US 20200051316) in par. [0333], teaches each compressed block in the acceleration structure hierarchy has children composed of multiple blocks of memory containing alpha primitives (whose intersection points require streaming processor computation to account for displacement).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUC N DOAN whose telephone number is (571)270-3397. The examiner can normally be reached Monday - Friday: 9am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Faulk Devona can be reached on (571) 272-7515. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUC N DOAN/Examiner, Art Unit 2618