Prosecution Insights
Last updated: May 29, 2026
Application No. 17/946,821

SELF-ALIGNED BACKSIDE CONTACT

Non-Final OA §103
Filed
Sep 16, 2022
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Non-Final)
84%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1114 granted / 1323 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
46 currently pending
Career history
1389
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.3%
+46.3% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1323 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see page 7-8, filed 12/19/2025, with respect to the rejections of claims 1-13 under 35 U.S.C. 103 as being unpatentable over Chu et al (US Publication No. 2021/0399099) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chu et al (US Publication No. 2021/0399099) and Huang et al (US Publication No. 2021/0202385) or Van Dal et al (US Publication 2022/0020666). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al (US Publication No. 2021/0399099) in view of Huang et al (US Publication No. 2021/0202385) or Van Dal et al (US Publication 2022/0020666). Regarding claim 1, Chu discloses a CMOS apparatus that comprises: a semiconductor substrate Fig 5, 20 that has a frontside and a backside opposite the frontside Fig 5; a first source/drain structure Fig 5, 225S, which is disposed at the frontside of the substrate Fig 5, wherein the first source/drain structure has a backside that contacts the frontside of the substrate Fig 5 and the first source/drain structure has a frontside that is opposite the backside of the first source/drain structure Fig 5; a frontside interconnect layer ¶0036, which is disposed at the frontside of the first source/drain structure Fig 16; a frontside contact that electrically connects the first source/drain structure to the frontside interconnect layer ¶0036; a second source/drain structure Fig 10, which is disposed at the frontside of the substrate Fig 10, wherein the second source/drain structure has a backside that is adjacent to the substrate and the second source/drain structure has a frontside that is opposite the backside of the second source/drain structure Fig 10; a backside interconnect layer Fig 16, 266, which is disposed at the backside of the substrate; a backside contact Fig 16, 260/262/264, electrically connects the second source/drain structure to the backside interconnect layer Fig 16; and a dielectric structure Fig 10, 250/252 that insulates first and second sides of the backside contact from the substrate Fig 16. Chu is silent on the specific shape of the dielectric structure. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Chu discloses all the limitations but silent on the backside contact penetrates the substrate. Whereas Huang discloses a backside contact Fig 19, 120, which penetrates the substrate Fig 19, 102 and electrically connects the second source/drain structure to the backside interconnect layer Fig 19; and a dielectric structure Fig 19,122 that insulates first and second sides of the backside contact from the substrate Fig 19. Van Dal also discloses a backside contact Fig 18A,170b, which penetrates the substrate Fig 18A, 110 ¶ 0025 and electrically connects the second source/drain structure to the backside interconnect layer Fig 20A; and a dielectric structure Fig 20A, 160 that insulates first and second sides of the backside contact from the substrate Fig 20A. Chu, Huang and Van Dal are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Chu and incorporate the teachings of Huang or Van Dal to improve interconnect isolation and ease in manufacturing. Regarding claim 2, Van Dal and Huang discloses a backside interlayer dielectric Van Dal -Fig 20A, 150, which is disposed between the substrate and the backside interconnect layer Van Dal -Fig 20A; Huang -Fig 19. Regarding claim 3, Huang discloses wherein the sigma-profiled dielectric structure and the backside contact penetrate both the substrate and the backside interlayer dielectric Fig 19-20A. Regarding claims 4 and 5, Chu discloses wherein the sigma-profiled dielectric structure is widest at an interface between the backside interlayer dielectric and the substrate or wherein the sigma-profiled dielectric structure is narrowest at an interface between the backside interlayer dielectric and the backside interconnect layer Fig 10-16. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 6,Chu discloses all the limitations but silent on the specific shape of the dielectric structure. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 7,Chu discloses shallow trench isolation that insulates third and fourth sides of the backside contact from adjacent contacts ¶0016. Regarding claim 8, Chu discloses a semiconductor substrate Fig 5, 20 that has a frontside and a backside opposite the frontside Fig 5; a source/drain structure Fig 5, which is disposed at the frontside of the substrate Fig 5, wherein the source/drain structure Fig 5,225 has a backside that is adjacent to the substrate and the source/drain structure has a frontside that is opposite the backside of the source/drain structure Fig 5; a backside interconnect layer Fig 16,266, which is disposed at the backside of the substrate Fig 16; a backside contact Fig 16,260/262/264, electrically connects the source/drain structure to the backside interconnect layer Fig 16; and a dielectric structure Fig 16, 250/252 that insulates first and second sides of the backside contact from the substrate Fig 16. Chu is silent on the specific shape of the dielectric structure. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Chu discloses all the limitations but silent on the backside contact penetrates the substrate. Whereas Huang discloses a backside contact Fig 19, 120, which penetrates the substrate Fig 19, 102 and electrically connects the second source/drain structure to the backside interconnect layer Fig 19; and a dielectric structure Fig 19,122 that insulates first and second sides of the backside contact from the substrate Fig 19. Van Dal also discloses a backside contact Fig 18A,170b, which penetrates the substrate Fig 18A, 110 ¶ 0025 and electrically connects the second source/drain structure to the backside interconnect layer Fig 20A; and a dielectric structure Fig 20A, 160 that insulates first and second sides of the backside contact from the substrate Fig 20A. Chu, Huang and Van Dal are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Chu and incorporate the teachings of Huang or Van Dal to improve interconnect isolation and ease in manufacturing. Regarding claim 9, Van Dal and Huang discloses a backside interlayer dielectric Van Dal -Fig 20A, 150, which is disposed between the substrate and the backside interconnect layer Van Dal -Fig 20A; Huang -Fig 19. Regarding claim 10, Huang discloses wherein the sigma-profiled dielectric structure and the backside contact penetrate both the substrate and the backside interlayer dielectric Fig 19-20A. Regarding claims 11 and 12, Chu discloses wherein the sigma-profiled dielectric structure is widest at an interface between the backside interlayer dielectric and the substrate or wherein the sigma-profiled dielectric structure is narrowest at an interface between the backside interlayer dielectric and the backside interconnect layer Fig 10-16. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 13,Chu discloses all the limitations but silent on the specific shape of the dielectric structure. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Sep 16, 2022
Application Filed
Apr 17, 2024
Response after Non-Final Action
Oct 24, 2025
Non-Final Rejection mailed — §103
Dec 19, 2025
Response Filed
Mar 24, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.2%)
1y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1323 resolved cases by this examiner. Grant probability derived from career allowance rate.

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