DETAILED ACTION
Claims 21-28 and 41-52 have been elected and examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The original disclosure is objected to because of the following informalities:
In paragraph 150, line 2, replace “DPE” with --DPEs-- for improve grammar.
The amended disclosure submitted on March 5, 2026, is objected to because of the following informalities:
In paragraph 1, line 5, the patent number is incomplete. Please insert “5” at the end.
Appropriate correction is required.
Drawings
Replacement FIG.6 submitted on March 5, 2026, is objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 640 and 658 in FIG.6 have both been used to designate 1/AV:X.
A corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. Please ensure the replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 26 is objected to because of the following informalities:
In line 2, delete “and”.
Claim 28 is objected to because of the following informalities:
In the last line, replace “registered couple” with --register coupled--.
Claim 41 (and similarly claim 46) is objected to because of the following informalities:
Insert --a-- before “convolutional” and before “pooling”.
Claim 42 (and similarly claim 47) is objected to because of the following informalities:
Insert --a-- before “fully”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claims 21, 43-45, and 48-51, a/the controller to perform the various claimed functions. A controller 502 is shown generically in FIG.5 and equated to a configuration optimizer (paragraph 123), mode selector (paragraph 129), convolution engine (paragraph 137), and fully-connected engine (paragraph 139). However, all of this constitutes generic disclosure, not specific structural disclosure required for 112(f) invocation. As such, broadest reasonable interpretation is taken for each claimed instance of “controller” and 112(a)/(b) rejections are set forth below. The examiner recommends claiming “controller circuit” to not invoke 112(f).
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-28 and 41-52 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 21, 43-45, and 48-51, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the controller to perform the claimed function(s). The specification does not demonstrate that applicant has made an invention that achieves the claimed function(s) because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-28 and 41-52 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 21, last paragraph, both instances of “the operation mode” since there are multiple operation modes in the 2nd to last paragraph.
In claims 43-44, “the operation mode” for similar reasoning.
In claim 44, “the neural network layer” because there are multiple in claim 21.
In claims 45 and 48-51, each instance of “the operation mode” for similar reasoning given above.
In claims 49 and 51-52, “the neural network layer” for similar reasoning given above.
Regarding claims 21, 43-45, and 48-51, the controller + function limitations invoke U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claims are indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
All dependent claims are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-28 and 41-52 are rejected under 35 U.S.C. 103 as being unpatentable over Simkins et al. (US 2006/0190516) (as cited by applicant) in view of Park (US 2018/0253635) (as cited by applicant).
Referring to claim 21, Simkins has taught a hardware accelerator comprising:
a data path element (DPE) (FIG.2, 114-2), the DPE comprising:
an accumulator (FIG.2, 1111 and/or P register receiving data from 1111),
a multiplier (FIG.2, note the ‘X’ to the left of the ‘M’ register in 114-2. The multiplication result is sent to the accumulator for accumulation),
a data input interface (FIG.2, at least the interface receiving at least A and B inputs 270, 272),
an additional data input interface (FIG.2, 276 and/or 278),
a first switch (FIG.2, note the mux (switch) receiving B 270 and input 282) coupled to the data input interface and the additional data interface (the switch receiving B 270 is coupled to the data input interface to receive B 270, and to the additional data interface 276), and
a second switch (FIG.2, the switch/mux following the two ‘B’ registers) coupled to the first switch (from FIG.2, this second switch’s top input is connected directly to the first switch prior to the two ‘B’ registers);
Simkins has not taught a controller coupled with the DPE, the controller to: determine an operation mode of the DPE by selecting the operation mode selected from a plurality of operation modes, the plurality of operation modes corresponding to different types of neural network layers, and configure the DPE to operate in the operation mode for executing a neural network layer corresponding to the operation mode. However, Park has taught a controller (FIG.16, 220) coupled to DPE circuits (FIG.16, 211, which are shown in more detail in FIG.17) that include, similarly to those in Simkins, a multiplier coupled to an accumulator, along with other logic that allows them to be configured to implement a selected one of multiple neural network layers (e.g. convolution or pooling) (paragraphs 153, 160, 162-164, and 174-177). This allows the same logic to be reconfigured for implementing different functions pertaining to artificial intelligence, thereby increasing flexibility and capability of the system. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Simkins to include a controller coupled with the DPE, the controller to: determine an operation mode of the DPE by selecting the operation mode selected from a plurality of operation modes, the plurality of operation modes corresponding to different types of neural network layers, and configure the DPE to operate in the operation mode for executing a neural network layer corresponding to the operation mode.
Referring to claim 22, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the additional data interface is coupled to the accumulator (from FIG.2, adjacent data interface 278 is coupled to accumulator 1111 via P register and associated switch/mux).
Referring to claim 23, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the data input interface is coupled to a multiplexer (from FIG.2, data input interface propagating input B 270 is coupled to the output of the mux preceding the two B registers, when selected by the mux, so as to pass input B to the B registers).
Referring to claim 24, Simkins, as modified, has taught the hardware accelerator of claim 21, further comprising an enable interface (e.g. FIG.2, 217, 218, 320, and/or 274), the enable interface coupled to the multiplier (input C goes into the Y or Z input (second input) of the multiplier) and to the controller (whatever sends input C is part of the controller).
Referring to claim 25, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the DPE further comprises:
a bypass selector interface coupled to the multiplier (from FIG.2, to the left of the multiplier, there is a bypass selector interface that provides A or B data, directly (in bypass mode), or indirectly through A and B registers);
a third switch coupled to the multiplier (from FIG.2, the switch/mux after the ‘M’ register is a third switch, which, at its top input, is coupled to a first direct output of the multiplier, and at its bottom input, is coupled to a second indirect output of the multiplier via the M register); and
a bypass interface coupled to the third switch (all switches/muxes have control interfaces to cause the switch to select one of multiple inputs. Thus, although not explicitly shown in FIG.2, the third switch include a bit interface to receive a control bit to select either the top or bottom input).
Referring to claim 26, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein and the DPE further comprises:
a third switch (FIG.2, X switch) coupled to accumulator (the output of the X switch is coupled to an input of accumulator 1111. Also, switch X receives, at its top input, an output of the accumulator via line 278); and
a bypass interface coupled to the third switch (see line 271, which is part of an interface that allows inputs A and B to bypass the multiplier).
Referring to claim 27, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the DPE further comprises:
a third switch (FIG.2, the switch to the immediate right of the M register) coupled to the multiplier (this switch is connected directly to the output of the multiplier and connected indirectly to the output of the multiplier (through the M register)) and to the accumulator (this switch sends data to the X input of the accumulator 1111 through the X switch); and
a fourth switch (FIG.2, the X switch) coupled to the third switch (the X switch is coupled to the third switch after the M register and receives data therefrom), and to the accumulator (the X switch is coupled to the X input of the accumulator 1111).
Referring to claim 28, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the DPE further comprises:
a third switch coupled to the accumulator (FIG.2, the switch after the P register);
a fourth switch coupled to the third switch (FIG.2, the X switch or Z switch);
a data output interface coupled to the fourth switch (both the X and Z switches have output interfaces to be able to provide data to the accumulator. Also, the control interfaces of these switches (to control what is selected for output) may be deemed data output interfaces); and
a registered couple to the third switch and the fourth switch (from FIG.2, the P register, which is directly coupled to the third switch to its immediate right and also to the fourth switch (e.g. the data in the P register is sent to the X switch)).
Referring to claim 41, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the different types of neural network layers comprise convolutional layer and pooling layer (see paragraph 153).
Referring to claim 42, Simkins, as modified, has taught the hardware accelerator of claim 41, wherein the different types of neural network layers further comprise fully-connected layer (see paragraphs 43 and 50, which set forth a fully-connected layer type).
Referring to claim 43, Simkins, as modified, has taught the hardware accelerator of claim 21, further comprising: a connection multiplexer, the connection multiplexer to select data stored in a memory and to provide the DPE with at least part of the selected data, wherein the controller is further to configure the connection multiplexer based on the operation mode (in Simkins, as modified, there would be a connection multiplexer (Park, FIG.17, 215) that selects data from memory 212 instead of from another data source based on the controller selecting pooling mode (paragraph 153)).
Referring to claim 44, Simkins, as modified, has taught the hardware accelerator of claim 21, wherein the controller is further to: determine a plurality of arrangements for the operation mode based on a partition of channels of the neural network layer (from at least paragraphs 44-47, operations are performed on each channel (a corresponding feature map (in FM1 in FIG.2)); and configure the DPE to execute at least one of the plurality of arrangements (a DPE will be configured to execute a first arrangement (corresponding dot product (multiple-accumulate) operations involving a first channel of the weight maps WM and the first channel of the first feature map (FM1). Another arrangement would include operations on channels of WM and FM1).
Claim 45 is mostly rejected for similar reasoning as claim 21. Simkins, alone or as modified, has further taught that the hardware accelerator comprises a data path element (DPE) array (see the multiple DPEs 114 in FIG.2 of Simkins as well as the multiple DPEs 211 in FIG.16 of Park), and configuring a plurality of DPEs in the DPE array to operate in the operation mode for executing a neural network layer corresponding to the operation mode (FIG.17 shows one DPE being configured. However, there are multiple DPEs 211 in FIG.16, and multiple may be configured to operate in parallel (FIGs.20,23 and paragraphs 178-186).
Claims 46-49 are rejected for similar reasoning as claims 41-44, respectively.
Referring to claim 50, Simkins, as modified, has taught the hardware accelerator of claim 49, wherein the controller is to determine the plurality of arrangements for the operation mode based on a number of available DPEs in the DPE array (from FIGs.20-23, in order to execute N arrangements in parallel, N DPEs must be available).
Referring to claim 51, Simkins, as modified, has taught the hardware accelerator of claim 49, wherein the controller is to determine the plurality of arrangements for the operation mode based on utilization of the DPE array for executing the neural network layer (from FIGs.20-23, in order to execute N arrangements in parallel, N DPEs must be available, i.e., not utilized).
Referring to claim 52, Simkins, as modified, has taught the hardware accelerator of claim 49, wherein the plurality of DPEs are to process at least some of the channels of the neural network layer in parallel (see FIGs.20-23 and the descriptions thereof).
Response to Arguments
Applicant argues that the prior art has not taught the claims as amended.
While Simkins alone does not teach the claims as amended, Simkins in view of Park does, as evidenced by the claim rejections above.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Falcon (US 2016/0026912) has taught reconfiguring circuits such that they are reused to perform operations for a convolution layer, pooling layer, and fully-connected layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights