CTNF 17/947,642 CTNF 92202 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 1 . Claim s 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Power et al (US 2021/0319317, herein Power) in view of Fok et al (US 2022/0012598, herein Fok) . In the following rejections, the embodiment of claim 11 will be addressed first. Regarding claim 11, Power teaches a compute block, the compute block associated with a first memory (Fig 1, computing system & data store) and comprising: a processing element configured to perform a multiply-accumulate (MAC) operation on an activation context and a weight context (Fig 2, [0075], accelerator 200 & MAC operations); a second memory for storing a non-zero valued activation in the activation context (Fig 2, [0079], activation data buffer); a third memory for storing a non-zero valued weight in the weight context (Fig 2, [0078], weight data buffer); and a sparsity decoder (Fig 2, combined sparsity controller 234) configured to: generate a combined sparsity vector with an activation sparsity vector with a weight sparsity vector, wherein the activation sparsity vector indicates positions of non-zero valued activations in the activation context, the weight sparsity vector indicates positions of non-zero valued weights in the weight context, and the combined sparsity vector comprises a zero valued bit and a non-zero valued bit ([0090], [0094-0097], combined sparsity controller to identify non-zero values and generate combined sparsity bit mask of activation & weight data); receive the non-zero valued activations and the non-zero valued weights from the first memory (Fig 2, [0085], obtain input activation & weight data); determine a position of a non-zero valued bit in the combined sparsity vector ([0094-0097], combined sparsity bit mask of non-zero values); determine a position for storing the non-zero valued activation in the second memory and for storing the non-zero valued weight in the third memory ([0078-0079], [0096], determine positions of non-zero values to be stored in activation and weight buffers). Power fails to teach wherein the sparsity decoder determines an address for storing the non-zero activation and weight values. Fok teaches a compute block comprising a memory and configured to determine an address for storing a non-zero valued activation and non-zero valued weight (Fig 6, [0075], local memory for weight values & [0078], [0099], storing non-zero activation vector values, [0059], [0079-0080], [0085-0090], determining address of valid non-zero input data). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Power and Fok to utilize explicit addressing for the non-zero input values of the exemplary MAC operations. While Power does not explicitly state that the location of weight or activation inputs may be placed at a specific memory address, Power does describe both the weight and activation data buffers as being implemented in a standard form of memory ([0086], volatile, non-volatile, or other memories). As accessing data from a standard type of memory such as those contemplated by Power is a routine and conventional aspect of the microprocessor art, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art. Regarding claim 12, the combination of Power and Fok teaches the compute block of claim 11, wherein the non-zero valued activations or the non-zero valued weights were stored at consecutive addresses in the first memory, and the consecutive addresses have been changed to inconsecutive addresses in a sequence of addresses (Fok [0053], [0079], representing non-zero values of consecutively addresses sparse vector, changed to address offset-based representation & Power [0090], [0094-0097], representing weight and activation sparse vectors). Regarding claim 13, the combination of Power and Fok teaches the compute block of claim 12, wherein: the consecutive addresses have been changed to the inconsecutive addresses in the sequence of addresses based on the activation sparsity vector or the weight sparsity vector, and positions of the inconsecutive addresses in the sequence of addresses match positions of non-zero valued bits in the activation sparsity vector or the weight sparsity vector (Fok [0053], [0079], representing non-zero values of consecutively addresses sparse vector, changed to address offset-based representation & Power [0090], [0094-0097], representing weight and activation sparse vectors). Regarding claim 14, the combination of Power and Fok teaches the compute block of claim 12, wherein a number of addresses in the sequence of addresses equals a number of activations in the activation context, and one or more addresses in the sequence of addresses do not store any data (Power [0090], [0094-0097], zero valued sparsity vector positions do not store data & Fok [0059], [0079-0080], [0085-0090], determining address of valid non-zero input data). Regarding claim 15, the combination of Power and Fok teaches the compute block of claim 11, wherein the first memory is outside the compute block (Power Figs 1&2, external data store to accelerator). Regarding claim 16, the combination of Power and Fok teaches the compute block of claim 11, wherein: the processing element comprises a first multiplier, a second multiplier, and an accumulator, the first multiplier is to perform a first multiplication operation on the non-zero valued activation and the non-zero valued weight, the second multiplier is to perform a second multiplication operation on another non-zero valued activation in the activation context and another non-zero valued weight in the weight context; and the accumulator is to accumulate a result of the first multiplication operation and a result of the second multiplication operation (Power Fig 2, [0079], [0098], [0230], multiplier-accumulator array for each input value from the weight & activation data buffers holding non-zero values). Regarding claim 17, the combination of Power and Fok teaches the compute block of claim 16, wherein the compute block further comprises a fourth memory for storing the another non-zero valued activation in the activation context and a fifth memory for storing the another non-zero valued weight in the weight context (Power Figs 1, 2, & 19, additional accelerator circuits 108, 110 each with local activation & weight data buffers). Regarding claim 18, the combination of Power and Fok teaches the compute block of claim 11, wherein the sparsity decoder is configured to determine the position of the non-zero valued bit in the combined sparsity vector by identifying the non-zero valued bit within a subset of the combined sparsity vector (Power [0090], [0094-0097], identify non-zero bits in weight and activation sparsity data to generate combined sparsity vector). Regarding claim 19, the combination of Power and Fok teaches the compute block of claim 18, wherein the sparsity decoder is configured to determine the position of the non-zero valued bit in the combined sparsity vector by: generating a vector based on the combined sparsity vector and a mask vector; generating a one-hot vector based on the vector, wherein the one-hot vector comprises one non-zero valued bit and a plurality of zero valued bits; and determining the position based on the one-hot vector (Power [0090-0091], [0097], bit mask vector using 1 bit of control to represent a byte of data representing non-zero value positions). Regarding claim 20, the combination of Power and Fok teaches the compute block of claim 19, wherein the sparsity decoder is further configured to determine a sequence of addresses in the second memory for the non-zero valued activations in the activation context, wherein determining the position based on the one-hot vector comprises determining the position based on the one-hot vector and gray codes so that two adjacent addresses in the sequence are different by one bit (Fok [0059], [0079-0080], [0085-0090], determining address of valid non-zero input data & Power [0090-0091], [0097], bit mask vector using 1 bit of control to represent a byte of data representing non-zero value positions). Claims 1-10 refer to a method embodiment of the compute block embodiment of claims 11-20. Therefore, the above rejections for claims 11-20 are applicable to claims 1-10. Claims 21-25 refer to a media embodiment of the method embodiment of claims 1, 2, 5, 8, and 9, respectively. Therefore, the above rejections for claims 1, 2, 5, 8, and 9 are applicable to claims 21-25, respectively . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ichiba (US 2023/0153261) discloses a processor for multiplying a sparse matrix vector stored at consecutive memory addresses. Baum (US 2020/0285950) discloses a processor for storing a sparse weight vector at consecutive locations in memory. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL J METZGER/ Primary Examiner, Art Unit 2183 Application/Control Number: 17/947,642 Page 2 Art Unit: 2183 Application/Control Number: 17/947,642 Page 3 Art Unit: 2183 Application/Control Number: 17/947,642 Page 4 Art Unit: 2183 Application/Control Number: 17/947,642 Page 5 Art Unit: 2183 Application/Control Number: 17/947,642 Page 6 Art Unit: 2183 Application/Control Number: 17/947,642 Page 7 Art Unit: 2183
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