DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 08/07/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 08/07/2025 in reply to the non-final rejection mailed on 06/03/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Applicant includes new claims 18-20. Accordingly, pending in this Office action are claims 7-20.
Claim Objections
Claim 7 is objected to because of the following formalities, incorrect spelling:
wherein the method is based on a Higk-K Metal Gate (HKMG) process,
“Higk-K” in line 17
the second gate comprise a second metal gate,
“comprise” in line 19
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7, 8, 11, 15, & 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 20060115940).
Regarding Claim 7, Kim (see, e.g., figs. 7a-7e) shows a method for preparing a semiconductor structure, comprising
providing a substrate 100,
comprising a PMOS region P and an NMOS region N;
sequentially forming a gate dielectric layer 106 (see, e.g., para.0060) and an initial work function layer 308 (see, e.g., para.0074) on the substrate;
performing a first doping treatment 315 (see, e.g., fig. 7d) on the initial work function layer of the PMOS region and adjusting a work function value of the initial work function layer of the PMOS region (see, e.g., para.0058),
to convert the initial work function layer of the PMOS region into a first work function film 310;
performing a second doping treatment 314 (see, e.g., fig. 7b) on the initial work function layer of the NMOS region and adjusting a work function value of the initial work function layer of the NMOS region (see, e.g., para.0058),
to convert the initial work function layer of the NMOS region into a second work function film 309;
forming a gate electrode film 116 (see, e.g., para.0066) on a surface of the first work function film and on a surface of the second work function film;
and etching the gate electrode film, the first work function film of the PMOS region, and the second work function film of the NMOS region (see, e.g., fig. 7d),
to form a first gate PMOS Gate Stack in the PMOS region and a second gate NMOS Gate Stack in the NMOS region (see, e.g., fig. 7d),
the first gate including a first work function layer 310’ and a first gate electrode layer 116’ that are stacked,
and the second gate including a second work function layer 309’ and a second gate electrode layer 116’ that are stacked.
wherein the method is based on a Higk-K Metal Gate (HKMG) process,
the gate dielectric layer comprises a high-k material (see, e.g., para.0060),
the first gate comprises a first metal gate 116’,
the second gate comprise a second metal gate 116’,
and the initial work function layer comprises no polysilicon
Regarding Claim 8, Kim (see, e.g., fig. 7a, fig. 7d, para.0063, para.0075) shows the method for preparing a semiconductor structure according to claim 7,
wherein before performing the first doping treatment and the second doping treatment, the method also comprises:
forming a buffer layer 110 on the surface of the initial work function layer;
and after the first doping treatment and the second doping treatment,
removing the buffer layer.
Regarding Claim 11, Kim (see, e.g., para.0075, para.0076) shows the method for preparing a semiconductor structure according to claim 7,
wherein the first doping treatment is performed by a first ion implantation process 315;
and/or the second doping treatment is performed by a second ion implantation process 314
Regarding Claim 15, Kim (see, e.g., para.0074) shows the method for preparing a semiconductor structure according to claim 7,
wherein a material of the initial work function layer comprises TiN.
Regarding Claim 18, Kim (see, e.g., fig. 1, para.0045, para.0074, claim 5) shows the method for preparing a semiconductor structure according to claim 7,
wherein a material of the initial work function layer comprises TaN or MoN.
Kim states the work function of a TaN layer to be 4.5 eV, the compatible work function range for the initial work function layer 308 to be between 4.4 and 4.7 eV, and the work function layer comprises at least one of molybdenum nitride (MoN) or tantalum nitride (TaN). Therefore, the material for the initial work function layer 308 can be TaN and Kim anticipates the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20060115940) in view of Xu (CN 104752202).
Regarding Claim 9, Kim shows the method for preparing a semiconductor structure according to claim 8.
Kim, however, fails to teach
wherein the buffer layer has a thickness of 2 nm to 7 nm
Xu (see, e.g., para.0079), in a similar method to Kim, shows a buffer layer that has thickness between 1-50 nm. Since the applicant has not established the criticality of the claimed range of buffer layer thickness, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of the thickness for the buffer layer of Xu in the method of Kim.
However, ranges of buffer layer thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Criticality
The specification contains no disclosure of either the critical nature of the claimed temperature and pressure ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20060115940) in view of Chau (US 20040222474).
Regarding Claim 10, Kim shows the method for preparing a semiconductor structure according to claim 7,
Kim, however, fails to show
wherein dopant ions used in the first doping treatment comprise
aluminum ions, cobalt ions, nickel ions, ruthenium ions, rhodium ions, palladium ions, rhenium ions, iridium ions or platinum ions,
and dopant ions used in the second doping treatment comprise
lanthanum ions, titanium ions, zirconium ions, tantalum ions, niobium ions or manganese ions.
Chau (see, e.g., para.0016, para.0021, para.0022), in a similar method to Kim, teaches that dopant ions such as titanium, aluminum, niobium, tantalum, zirconium, platinum, palladium, & ruthenium are suitable materials for adjusting the work function.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the dopant ions such as titanium, aluminum, niobium, tantalum, zirconium, platinum, palladium, & ruthenium of Chau, in the work function layer doping treatments of Kim, as suitable materials for adjusting the work function.
Claims 12 & 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20060115940) in view of Zhu (US 20150048458).
Regarding Claim 12, Kim shows the method for preparing a semiconductor structure according to claim 11,
Kim, however, fails to show
wherein process parameters of the first ion implantation process comprise:
implanted ions being aluminum ions,
implanted energy of the aluminum ions being 0.1 keV to 16 keV,
and an implanted dose of the aluminum ions being 1e14 to 5e16/cm2.
Zhu (see, e.g., para.0033, para.0034), in a similar method to Kim, teaches that aluminum dopant ions are a suitable material for adjusting the work function.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the aluminum dopant ions of Zhu, in the work function layer doping treatments of Kim, as a suitable material for adjusting the work function.
Zhu (see, e.g., para.0033), in a similar method to Kim, in view of Chau, shows ion implantation performed with an implanted energy of aluminum ions between 0.2 keV to 30 keV and an implanted dose of aluminum ions between 1e13 to 1e15/cm2.
Since the applicant has not established the criticality of the claimed ranges of implanted energy and the implanted dose, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of Zhu in the method of Kim.
However, ranges of implanted energy and implanted dose concentration will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical (see paragraph 19 for criticality statement). “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Regarding Claim 13, Kim shows the method for preparing a semiconductor structure according to claim 11,
Kim, however, fails to show
wherein process parameters of the second ion implantation process comprise:
implanted ions being lanthanum ions,
implanted energy of the lanthanum ions being 0.1 keV to 20 keV,
and an implanted dose of the lanthanum ions being 1e14 to 5e16/cm2.
Zhu (see, e.g., para.0032, para.0034), in a similar method to Kim, teaches that lanthanum dopant ions are a suitable material for adjusting the work function.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the lanthanum dopant ions of Zhu, in the work function layer doping treatments of Kim, as a suitable material for adjusting the work function.
Zhu (see, e.g., para.0032), in a similar method to Kim, in view of Chau, shows ion implantation performed with an implanted energy of lanthanum ions between 0.2 keV to 30 keV and an implanted dose of lanthanum ions between 1e13 to 1e15/cm2.
Since the applicant has not established the criticality of the claimed ranges of implanted energy and the implanted dose, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of Zhu in the method of Kim.
However, ranges of implanted energy and implanted dose concentration will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical (see paragraph 19 for criticality statement). “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20060115940) in view of Bu (US 20080268623).
Regarding Claim 14, Kim shows the method for preparing a semiconductor structure according to claim 7,
Kim, however, fails to show
wherein the first doping treatment is performed by a thermal diffusion process;
and/or the second doping treatment is performed by a thermal diffusion process.
Bu (see, e.g., para.0012), in a similar method to Kim, teaches that thermal diffusion as a doping treatment would lead to higher dopant activation, suppress excess dopant diffusion, and improve semiconductor performance.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the thermal diffusion of Bu in the method of Kim to obtain higher dopant activation, suppress excess dopant diffusion, and improve semiconductor performance.
Claims 16, 17, 19, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20060115940), in view of Bohr (US 20110156107) and Beyer (US 20120292637), and further in view of Rodder (US 4877755).
Regarding Claim 16, Kim (see, e.g., para.0066) shows the method for preparing a semiconductor structure according to claim 7,
wherein the gate electrode film comprises
a polysilicon film,
a conductive film,
that are sequentially stacked
Kim (see, e.g., para.0066) states 116 is a conductive layer that can comprise polysilicon, a refractory metal, and/or a refractory metal silicide. Thus, 116 comprises a polysilicon film and a conductive film.
Kim, however, fails to show
wherein the gate electrode film comprises
the polysilicon film,
a barrier film
the conductive film,
and a protective film
that are sequentially stacked;
Bohr (see, e.g., para.0038-0039), in a similar method to Kim, teaches that a protective film, sequentially stacked on the conductive film, as part of the gate electrode film would protect the conductive film during subsequent etching and prevent unwanted electrical shorting.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the protective film of Bohr, in the method of Kim, to protect the conductive film during subsequent etching and prevent unwanted electrical shorting.
Beyer (see, e.g., fig. 1d, para.0029), in a similar method to Kim, in view of Bohr, shows a configuration including:
wherein the gate electrode film comprises:
a polysilicon film 110
a protective film 112 & 113
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Beyer, in the method of Kim, in view of Bohr, since Beyer shows a known configuration to implement the protective film.
Rodder (see, e.g., pg. 7, col. 7, lines 15-19), in a similar method to Kim, in view of Bohr & Beyer, teaches that a silicide barrier film, on a silicide conductive film, would prevent the unwanted expansion of a conductive silicide film.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the
silicide barrier film of Rodder, sequentially stacked between the polysilicon and protective film of the method of Kim, in view of Bohr & Beyer, to prevent the unwanted expansion of the conductive silicide film.
Thus, Kim, in view of Bohr and Beyer (see, e.g., fig. 1b-1c, para.0027-29), and further in view of Rodder, shows the remaining limitations of claim 16:
and process steps for forming the first gate and the second gate comprise:
forming a patterned photoresist layer 125 on a surface of the protective film;
etching, using a dry etching process,
the polysilicon film,
the barrier film,
the conductive film,
the protective film,
the first work function film,
and the second work function film
of both the PMOS region and the NMOS region by using the patterned photoresist layer as a mask;
and removing the patterned photoresist layer.
Regarding Claim 17, Kim (see, e.g., fig. 7e, para.0078), in view of Bohr and Beyer, and further in view of Rodder, shows the method for preparing a semiconductor structure according to claim 16,
wherein after forming the first gate and the second gate, the method further comprises:
forming a spacer layer 118 between the first gate and the second gate;
and forming source and drain regions 120N & 120P on both sides of the first gate and the second gate.
Regarding Claim 19, Kim (see, e.g., fig. 7e) , in view of Bohr and Beyer, and further in view of Rodder, shows the method for preparing a semiconductor structure according to claim 16,
wherein a top surface of the first gate is flush with a top surface of the second gate.
Regarding Claim 20, Kim, in view of Bohr and Beyer (see, e.g., para.0029), and further in view of Rodder (see, e.g., pg. 7, col. 7, lines 15-19), shows the method for preparing a semiconductor structure according to claim 16,
wherein a material of the barrier film comprises metal silicide
and a material of the protective film comprises silicon dioxide or silicon nitride.
Response to Arguments
Applicant’s arguments with respect to claim(s) 7-17 have been considered but are moot because the new grounds of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the arguments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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