DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/22/2026 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 1/22/2026. Claims 1-6, 8, 21-26 & 28-30 are pending in this application. Claims 7, 9-20 & 27 are canceled. Claims 29-30 are new.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-4, 6, 8, 21-24, 26 and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Burke et al. (US 2010/0123192) in view of Jang et al. (US 5,786,260) and Kitazawa et al. (US 2003/0157755).
Re claim 1, Burke teaches, under BRI, Figs. 6-12, [0037, 0040, 0042, 0047-0052], a method of semiconductor processing, the method comprising:
-forming a first recess (120) and a second recess (124) in a semiconductor substrate (100), wherein the first recess (120) is formed in a first die area (12) of the semiconductor substrate (100) and the second recess (124) is formed in an area (14) of the semiconductor substrate (100), wherein the area (14) is disposed laterally between the first die area (12) and a second die area (16, 18) that neighbors the first die area (12);
-forming a first conformal dielectric layer (152) in the first recess (120) and the second recess (124) and over the semiconductor substrate (100);
-forming a first fill material (154) over the first conformal dielectric layer (152) in the first recess (120) and over the first conformal dielectric layer (152) in the second recess (124), the first fill material filling (154) at least the first recess (120) over the first conformal dielectric layer (152) (Fig. 7);
-recessing the first fill material (154) in the first recess (120) and the first fill material (154) in the second recess (124) (Fig. 9);
-etching (e.g., further recessed) the recessed first fill material (154) in the first recess (120) and the recessed first fill material (154) in the second recess (124) (Fig. 11); and
-etching exposed portions of the first conformal dielectric layer (152) (Fig. 12).
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Burke does not explicitly teach the second recess is formed in an alignment mark area of the semiconductor substrate, wherein the alignment mark area is disposed laterally between the first die area and the second die area that neighbors the first die area.
Jang teaches, Fig. 2A, abstract, the second recess (48) is formed in an alignment mark area (30) of the semiconductor substrate (10), wherein the alignment mark area (30) is disposed laterally between the first die area (12) and the second die area (12) that neighbors the first die area (12).
As taught by Jang, one of ordinary skill in the art would utilize & modify the above teaching into Burke to obtain the second recess is formed in an alignment mark area of the semiconductor substrate, wherein the alignment mark area is disposed laterally between the first die area and a second die area that neighbors the first die area as claimed, because it aids in reducing process cost and yield loss. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Jang in combination with Burke due to above reason.
Jang teaches photolithography process and alignment mark (Fig. 2A, col. 2, 3rd par., & claim 5), but Burke/Jang does not explicitly teach etching, in accordance with a photolithography process, wherein the photolithography process uses (*) the second recess including the first conformal dielectric layer and the recessed first fill material as an alignment mark.
Kitazawa teaches, Figs. 2-10, abstract, [0026, 0035, 0037, 0060], etching, in accordance with a photolithography process, wherein the photolithography process uses (*) the second recess (7 or 17) including the first conformal dielectric layer (9) and the recessed first fill material (30) as an alignment mark.
As taught by Kitazawa, one of ordinary skill in the art would utilize & modify the above teaching to obtain the photolithography process that uses the second recess including the first conformal dielectric layer and the recessed first fill material as an alignment mark as claimed, because the common purpose of an alignment mark is recognized in the art & it aids in preventing a decrease in alignment accuracy during a photolithography process.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kitazawa in combination with Burke/Jang due to above reason.
(*) The limitation “…the photolithography process uses the second recess…as an alignment mark” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 2, Burke teaches a width of the first recess (120) is equal to a width of the second recess (Fig. 6).
Re claim 3, in combination cited above, Kitazawa teaches a width of the first recess (27) is less than a width of the second recess (7) (Fig. 2).
Re claim 4, Burke teaches forming the first fill material (154) over the first conformal dielectric layer (152) in the second recess (124) fills the second recess over the first conformal dielectric layer (152) with the first fill material (154) (Fig. 7).
Re claim 6, Burke/Jang/Kitazawa does not explicitly teach during etching the recessed first fill material, a patterned photoresist is disposed over the semiconductor substrate, no portion of the patterned photoresist being disposed directly over the first recess during etching the recessed first fill material, no portion of the patterned photoresist being disposed directly over the second recess during etching the recessed first fill material.
Burke does teach the use of a patterned photoresist (151) disposed over the semiconductor substrate (100) during recessing the first fill material (154) (Figs. 8-9, [0048]) & a patterned photoresist (174) during removing portion of fill material (164) (Figs. 16-17, [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Burke to obtain, during etching the recessed first fill material, a patterned photoresist is disposed over the semiconductor substrate, no portion of the patterned photoresist being disposed directly over the first recess during etching the recessed first fill material, no portion of the patterned photoresist being disposed directly over the second recess during etching the recessed first fill material as claimed, because photoresist mask is known and widely used in the art, during etching, to protect underlying layers and obtain desired etched pattern(s). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Re claim 8, Burke teaches, Figs. 13-16, forming a second conformal dielectric layer (160) over the recessed first fill material (154) and the first conformal dielectric layer (152) in the first recess (120) and over the recessed first fill material (154) and the first conformal dielectric layer (152) in the second recess (124); and
forming a second fill material (164) over the second conformal dielectric layer (160) in the first recess (120) and over the second conformal dielectric layer (160) in the second recess (124), the second fill material (164) filling the first recess (120) over the second conformal dielectric layer (160), the second fill material (164) filling the second recess (124) over the second conformal dielectric layer (160), wherein the first conformal dielectric layer (152), the recessed first fill material (154), the second conformal dielectric layer (160), and the second fill material (164) in the first recess (120) form an isolation structure (as intended use and/or based on similar teaching) in the semiconductor substrate (100).
Re claim 29, in combination cited above, Kitazawa teaches, Figs. 2-10, abstract, [0026, 0028, 0035, 0037, 0060], forming the first recess (17a) and the second recess (7a) comprises: forming a third recess (7b) in a second alignment mark area (middle region) of the semiconductor substrate (1), wherein the first conformal dielectric layer (9) and the first fill material (30) are formed and recessed in the third recess (7b), and wherein etching the recessed first fill material (30) in accordance with the photolithography process comprises: using (*) the second recess (7a) to align a photomask (consider 4 or 6) in a first direction (x axis) and using (*) the third recess (7b) to align the photomask (4) in a second direction (y axis) perpendicular to the first direction.
(*) The limitation “…using the second recess…using the third recess…” is/are merely a functional/intended use limitation(s) that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 21, Burke teaches, under BRI, Figs. 6-12, [0037, 0040, 0042, 0047-0052], a method of semiconductor processing, the method comprising:
-forming a first trench (120) and a second trench (124) in a semiconductor substrate (100), wherein the first trench (120) is formed in a first die area (12) of the semiconductor substrate (100) and the second trench (124) is formed in an area (14) of the semiconductor substrate (100), wherein the area (14) is disposed laterally between the first die area (12) and a second die area (16, 18) that neighbors the first die area (12);
-forming a first conformal dielectric layer (152) in the first trench (120) and the second trench (124) and over the semiconductor substrate (100);
-forming a first fill material (154) over the first conformal dielectric layer (152) in the first recess (120) and over the first conformal dielectric layer (152) in the second trench (124), the first fill material filling (154) at least the first trench (120) over the first conformal dielectric layer (152) (Fig. 7);
-recessing the first fill material (154) in the first trench (120) and the first fill material (154) in the second trench (124) to below a top surface of the first conformal dielectric layer (152) (Fig. 9);
-etching (e.g., further recessed) the recessed first fill material (154) in the first trench (120) and the recessed first fill material (154) in the second trench (124) (Fig. 11); and
-etching exposed portions of the first conformal dielectric layer (152) (Fig. 12).
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Burke does not explicitly teach the second trench is formed in an alignment mark area of the semiconductor substrate, wherein the alignment mark area is disposed laterally between the first die area and the second die area that neighbors the first die area.
Jang teaches, Fig. 2A, abstract, the second trench (48) is formed in an alignment mark area (30) of the semiconductor substrate (10), wherein the alignment mark area (30) is disposed laterally between the first die area (12) and the second die area (12) that neighbors the first die area (12).
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As taught by Jang, one of ordinary skill in the art would utilize & modify the above teaching into Burke to obtain the second trench is formed in an alignment mark area of the semiconductor substrate, wherein the alignment mark area is disposed laterally between the first die area and a second die area that neighbors the first die area as claimed, because it aids in reducing process cost and yield loss. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Jang in combination with Burke due to above reason.
Jang teaches photolithography process and alignment mark (Fig. 2A, col. 2, 3rd par., & claim 5), but Burke/Jang does not explicitly teach etching, in accordance with a photolithography process, wherein the photolithography process uses (*) the second trench including the first conformal dielectric layer and the recessed first fill material as an alignment mark.
Kitazawa teaches, Figs. 2-10, abstract, [0026, 0035, 0037, 0060], etching, in accordance with a photolithography process, wherein the photolithography process uses (*) the second trench (7 or 17) including the first conformal dielectric layer (9) and the recessed first fill material (30) as an alignment mark.
As taught by Kitazawa, one of ordinary skill in the art would utilize & modify the above teaching to obtain the photolithography process that uses the second recess including the first conformal dielectric layer and the recessed first fill material as an alignment mark as claimed, because the common purpose of an alignment mark is recognized in the art & it aids in preventing a decrease in alignment accuracy during a photolithography process.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kitazawa in combination with Burke/Jang due to above reason.
(*) The limitation “…the photolithography process uses the second trench…as an alignment mark” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 22, Burke teaches a width of the first trench (120) is equal to a width of the second trench (124) (Fig. 6).
Re claim 23, in combination cited above, Kitazawa teaches a width of the first recess (27) is less than a width of the second recess (7) (Fig. 2).
Re claim 24, Burke teaches forming the first fill material (154) over the first conformal dielectric layer (152) in the second trench (124) fills the second trench over the first conformal dielectric layer (152) with the first fill material (154) (Fig. 7).
Re claim 26, Burke/Jang/Kitazawa does not explicitly teach during etching the recessed first fill material, a patterned photoresist is disposed over the semiconductor substrate, no portion of the patterned photoresist being disposed directly over the first recess during etching the recessed first fill material, no portion of the patterned photoresist being disposed directly over the second recess during etching the recessed first fill material.
Burke does teach the use of a patterned photoresist (151) disposed over the semiconductor substrate (100) during recessing the first fill material (154) (Figs. 8-9, [0048]) & a patterned photoresist (174) during removing portion of fill material (164) (Figs. 16-17, [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Burke to obtain, during etching the recessed first fill material, a patterned photoresist is disposed over the semiconductor substrate, no portion of the patterned photoresist being disposed directly over the first recess during etching the recessed first fill material, no portion of the patterned photoresist being disposed directly over the second recess during etching the recessed first fill material as claimed, because photoresist mask is known and widely used in the art, during etching, to protect underlying layers and obtain desired etched pattern(s). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Re claim 27, Burke teaches, under BRI, Figs. 8-9, aligning a photomask (151) relative to the semiconductor substrate (100) using the second trench as the alignment mark (as intended use/based on similar teaching), wherein the second trench (124) includes the first conformal dielectric layer (152) and the recessed first fill material (154) disposed therein.
Re claim 28, Burke teaches, Figs. 13-16, forming a second conformal dielectric layer (160) over the recessed first fill material (154) and the first conformal dielectric layer (152) in the first trench (120) and over the recessed first fill material (154) and the first conformal dielectric layer (152) in the second trench (124); and
forming a second fill material (164) over the second conformal dielectric layer (160) in the first trench (120) and over the second conformal dielectric layer (160) in the second trench (124), the second fill material (164) filling the first trench (120) over the second conformal dielectric layer (160), the second fill material (164) filling the second trench (124) over the second conformal dielectric layer (160), wherein the first conformal dielectric layer (152), the recessed first fill material (154), the second conformal dielectric layer (160), and the second fill material (164) in the first trench (120) form an isolation structure (as intended use and/or based on similar teaching) in the semiconductor substrate (100).
Re claim 30, in combination cited above, Kitazawa teaches, Figs. 2-10, abstract, [0026, 0028, 0035, 0037, 0060], forming the first trench (17a) and the second trench (7a) comprises: forming a third trench (7b) in a second alignment mark area (middle region) of the semiconductor substrate (1), wherein the first conformal dielectric layer (9) and the first fill material (30) are formed and recessed in the third recess (7b), and wherein etching the recessed first fill material (30) in accordance with the photolithography process comprises: using (*) the second trench (7a) to align a photomask (consider 4 or 6) in a first direction (x axis) and using (*) the third trench (7b) to align the photomask (4) in a second direction (y axis) perpendicular to the first direction.
(*) The limitation “…using the second trench…using the third trench…” is/are merely a functional/intended use limitation(s) that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
4. Claims 5 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Burke/Kitazawa as modified by Jang as applied to claims 1 & 21 above, and in view of Bergami et al. (US 4,871,689).
The teachings of Burke/Jang/Kitazawa have been discussed above.
Re claims 5 & 25, Burke/Jang/Kitazawa does not explicitly teach after forming the first fill material over the first conformal dielectric layer in the second recess, the first fill material over the first conformal dielectric layer in the second recess has a seam in the second recess.
Bergami teaches, Fig.3, after forming the first fill material (52) over the first conformal dielectric layer (51) in the second recess or trench, the first fill material (52) over the first conformal dielectric layer (51) in the second recess or trench has a seam (72) in the second recess or trench (42).
As taught by Bergami, one of ordinary skill in the art would utilize & modify the above teaching to obtain after forming the first fill material over the first conformal dielectric layer in the second recess, the first fill material over the first conformal dielectric layer in the second recess has a seam in the second recess as claimed, because a seam is recognized as result of conformal deposition of a material within trench/recess and it aids in improving characteristics of integrated circuit(s).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Bergami in combination with Burke/Jang/Kitazawa due to above reason.
Response to Arguments
5. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/7/26
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