DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 3/18/25, of Group I, in the reply filed on 4/14/25 was acknowledged in a previous office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-8, and 21-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0108998 A1 (“Chandolu”) in view of US 9136130 B1 (“Wada”).
Chandolu teaches, for example:
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Chandolu teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A semiconductor device, comprising:
a plurality of memory blocks (see e.g. para 68), each memory block comprising: a memory deck a first memory deck (e.g. one or more tiers 904 at or near the bottom of stack structure 902), the first memory deck comprising interleaved first conductor layers (e.g. 906 in Fig. 11A) and first dielectric layers (e.g. 104 in Fig. 11A); and
a first channel structure (e.g. portion of pillars 602 in the tiers of 904 at or near the bottom of stack structure 902, see para 117, and also see Figs. 15A-15D) extending through the first memory deck, the first channel structure comprising a first memory film (see below) and a first semiconductor channel (e.g. 1512),
wherein the first memory film comprises:
a tunneling layer (comprising e.g. 1526 in Fig. 15C, see e.g. para 131; 1526 is repeated multiple times over the “strings of memory cells” see e.g. para 117) over the first semiconductor channel,
a storage layer (e.g. 1528 in Fig. 15C, see e.g. para 131) over the tunneling layer, and
a blocking layer (e.g. 1530 in Fig. 15C, see e.g. para 131) over the storage layer,
wherein the storage layer is divided by the first dielectric layers into a plurality of sections (see e.g. Figs. 11A and 15C);
wherein the tunneling layer is in direct contact with multiple isolated sections of the storage layer (the tunneling layer is not particularly geometrically limited, e.g. it is not limited to being continuous, discontinuous, to have certain thicknesses or dimensions; thus, it is reasonable to interpret the tunneling layer as comprising multiple discontinuous sections 1526 all along the strings of memory cells; thus, each discontinuous portion of the tunneling layer directly contacts each isolated blocking layer);
a separation structure (e.g. structure in region 116 of Fig. 11A) extending to separate two adjacent memory blocks, each separation structure comprising:
a dielectric stack comprising interleaved third dielectric layers (104 in 116) and fourth dielectric layers (e.g. 502 in 116),
wherein
the third dielectric layers are in contact with the first dielectric layers (Fig. 11A), and
the fourth dielectric layers are in contact with the first conductor layers (Fig. 11A).
Chandolu does not explicitly teach that a continuous section of the tunneling layer is in direct contact with the multiple isolated sections of the storage layer.
Rather, Chandolu teaches at least four different geometries of the memory cells (see Figs. 15A-15D), i.e. four different geometries of the tunnel dielectric and storage layer. Hence, one of ordinary skill in the art would recognize that the exact geometry of the memory cell is not critical or unobvious.
Furthermore, Wada teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Chandolu, that a continuous section of the tunneling layer 11 is in direct contact with the multiple isolated sections of the storage layer 9 (see e.g. Fig. 1A, and see e.g. col 2 lines 51-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Wada to the invention of Chandolu. The motivation to do so is that the combination produces the predictable results of utilizing a geometry of the memory cell that increases data retention (see e.g. col 2 lines 53-58).
Chandolu and Wada together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The semiconductor device of claim 1, wherein the memory deck comprises:
a second memory deck (e.g. one or more tiers 904 at or near the top of stack structure 902) comprising interleaved second conductor layers 906 and second dielectric layers 104 above the first memory deck.
3. The semiconductor device of claim 2, further comprising:
a second channel structure (e.g. portion of pillars 602 in the tiers of 904 at or near the top of stack structure 902, see para 117, and also see Figs. 15A-15D) extending through the second memory deck, the second channel structure comprising a second memory film (e.g. 1516 in Fig. 15A) and a second semiconductor channel (e.g. 1512 in Fig. 15A),
wherein the second semiconductor channel is in contact with the first semiconductor channel (Fig. 11A).
5. The semiconductor device of claim 3, wherein the second memory film comprises
a tunneling layer (e.g. 1514 in Fig. 15A) over the second semiconductor channel,
a storage layer (e.g. 1516 in Fig. 15A) over the tunneling layer, and
a blocking layer (e.g. one or both of 1518 and/or 1520 in Fig. 15A) over the storage layer,
wherein the storage layer is divided by the second dielectric layers into a plurality of sections (Figs. 11A and 15A) (see also Fig. 1A of Wada).
6. The semiconductor device of claim 1, further comprising: a peripheral circuit (see e.g. para 137-145 and Fig. 16) disposed above or beneath the plurality of memory blocks.
7. The semiconductor device of claim 1, wherein the first conductor layers comprise a first portion near the separation structure and a second portion away from the separation structure, and the first portion and the second portion have a same thickness (see e.g. Figs. 11A and 15A).
8. The semiconductor device of claim 1, wherein the first dielectric layers comprise a first portion near the separation structure and a second portion away from the separation structure (see e.g. Figs. 11A and 15A), and a thickness difference between the first portion and the second portion is less than 1 nanometer (they have the same thickness as shown).
21. The semiconductor device of claim 1, wherein the first dielectric layers and the third dielectric layers are formed in a same process (see Fig. 1A and para 61-63).
22. The semiconductor device of claim 1, wherein the fourth dielectric layers electrically isolate the first conductor layers in two different memory blocks (see Fig. 11A).
23. The semiconductor device of claim 1, wherein the blocking layer is disposed between the storage layer and the first dielectric layer (see e.g. Fig. 15A).
24. The semiconductor device of claim 23, wherein the storage layer is divided by the first dielectric layers and the blocking layer into the plurality of isolated sections (see e.g. Figs. 11A and 15A).
25. The semiconductor device of claim 23, wherein the blocking layer is divided by the first dielectric layers (see e.g. Figs. 11A and 15A).
26. The semiconductor device of claim 23, wherein each of the first conductor layers further comprises a barrier layer (e.g. 1520 in Fig. 15A; or 1524 in Fig. 15B, or 1528 or 1530 in Fig. 15C).
27. The semiconductor device of claim 26, wherein the barrier layer is deposited between the fourth dielectric layers and the first conductive layers (see e.g. Figs. 15B and 15C).
28. The semiconductor device of claim 26, wherein the barrier layer comprises a TiN layer (see para 129).
29. The semiconductor device of claim 26, wherein the blocking layer and the barrier layer are disposed between the storage layer and the first dielectric layer (see e.g. Figs. 15A-15C).
30. The semiconductor device of claim 26, wherein the storage layer in two adjacent isolated sections of the plurality of isolated sections is divided by two blocking layers, two barrier layers, and one first dielectric layer (see e.g. Figs. 11A wherein there are two 602s in adjacent sections, each would have the structure shown in e.g. Fig. 15A, so the storage layers would be separated by at least two 1518s, two 1520s, and two 104s).
31. The semiconductor device of claim 26, wherein the tunneling layer covers the blocking layer, the barrier layer, the storage layer, and the first dielectric layer (see e.g. Figs. 15A-15C, wherein 1514 covers all the layers to its right).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896