Prosecution Insights
Last updated: April 19, 2026
Application No. 17/948,586

THIN FILM CAPACITORS

Non-Final OA §102
Filed
Sep 20, 2022
Examiner
DIAZ, JOSE R
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
799 granted / 922 resolved
+18.7% vs TC avg
Moderate +8% lift
Without
With
+7.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
948
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 922 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I in the reply filed on December 26, 2025 is acknowledged. Drawings The drawings were received on September 20, 2022. These drawings are acceptable. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 14 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kamgaing et al. (US 2022/0406523). Regarding claim 14, Kamgaing discloses a method of in-situ forming a three-dimensional (3D) capacitor on a package, the method comprising: forming a through glass via (TGV) (220) in a glass core (202) [Fig. 2]; forming a first electrode (206) (i) conformally depositing a dielectric material (208) directly on the first electrode, the dielectric material extending vertically and horizontally [Fig. 2 and paragraph 0032]; and forming a second electrode (210) on and in contact with the dielectric material [Fig. 2]. Regarding claim 17, Kamgaing discloses wherein forming the first electrode (206) includes forming the first electrode (206) at least partially in the BTGV (204) adjacent to the TGV (220) [Fig. 2]. Allowable Subject Matter Claims 1-6, 8, 13, and 19-20 are allowed. Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Duong et al. (US 2023/0091666) discloses a TGV (234/236) and a capacitor (210) [Fig. 2]. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Sep 20, 2022
Application Filed
Apr 17, 2023
Response after Non-Final Action
Feb 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 07, 2026
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SEMICONDUCTOR MEMORY DEVICE
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Patent 12588226
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Patent 12578645
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Patent 12581667
MULTISTACK METAL-INSULATOR-METAL (MIM) STRUCTURE USING SPACER FORMATION PROCESS FOR HETEROGENEOUS INTEGRATION WITH DISCRETE CAPACITORS
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 922 resolved cases by this examiner. Grant probability derived from career allow rate.

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