DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Previously objected: Claim 6 is objected to because of the following informalities: claim 6 is missing a period (.) at the end. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki et al. (US 2005/0263863, newly cited, hereinafter, Sasaki.)
In regard to claim 1, in figs. 1-16, for example, Sasaki discloses a semiconductor device structure 1 (para [0060]) comprising:
a semiconductor IC 3 (para [0061]) including a semiconductor integrated circuit (memory circuits, for example, fig. 1), a first IC terminal and a second IC terminal 3c (para [0063]);
a capacitor element 15 (para [0079], and fig. 16, for example) including a first terminal and a second terminal;
a support portion (substrate 8, para [0063]), including a support region with a principal surface that supports the capacitor element and the semiconductor IC, fig, 18;
a first conductor and a second conductor, or wires, 6 (para [0063]) that extend so as to connect the first terminal and second terminal of the capacitor element with, respectively, the first IC terminal and second IC terminal of the semiconductor IC (note: the second connection through Vss, see fig. 16); and
a sealing body 7 (para [0063], and figs. 16 and 28) that encloses the capacitor element, the semiconductor IC, the first conductor, the second conductor and the support region,
wherein, in a plan view, the first IC terminal and second IC terminal of the semiconductor IC, the first terminal and second terminal of the capacitor element, the first conductor and the second conductor are disposed at the inner side relative to an outer edge of the principal surface of the support region,
the semiconductor integrated circuit includes an internal circuit and a voltage regulator that provides power to the internal circuit (figs. 14 and 21-22, and para [0080]),
the voltage regulator has an output that is connected to the first IC terminal,
an electrical connection including the first IC terminal of the semiconductor IC, the first conductor, the first terminal of the capacitor element, the second terminal of the
capacitor element, the second conductor and the second IC terminal of the semiconductor IC is electrically closed by the semiconductor integrated circuit creating an antenna 12 (fig. 1 and para [0069].)
Regarding claim 2, wherein the support portion includes a lead frame (para [0047] and fig. 23, for example), the lead frame includes a die pad, the die pad being the support region, and a plurality of lead terminals 5a spaced apart from the die pad, and the sealing body includes resin that seals in the capacitor element, the semiconductor IC, the first conductor, the second conductor and the die pad.
Regarding claim 3, wherein at least one of the plurality of lead terminals is inflected in a first direction toward the capacitor element from the die pad. Fig. 1, for example.
Regarding claim 4, wherein all of the plurality of lead terminals are inflected in a first direction toward the capacitor element from the die pad. Fig. 1.
Regarding claim 5, wherein the first conductor includes a bonding wire that directly connects the first IC terminal of the semiconductor IC with the first terminal of the capacitor element. Fig. 16.
Regarding claim 6, wherein the second conductor includes a bonding wire that directly connects the second IC terminal of the semiconductor IC with the principal surface (where the Vss is formed) of the support region, and the second terminal of the capacitor element is connected with the principal surface of the support region by a conductive adhesive, solder connection, for example, (para [0065]).)
Regarding claim 7, as mentioned above, wherein the second conductor includes a bonding wire 6 that electrically directly connects the second IC terminal of the semiconductor IC with the second terminal of the capacitor element through Vss, Fig. 16.
Regarding claim 13, as mentioned above, wherein the electrical connection closed by the semiconductor integrated circuit forms a loop-shaped antenna 12 (fig. 1 and para [0069].)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki as applied to claim 1 above, and further in view of SHIMOYAMA et al. (US 2019/0088577, previously cited, hereinafter, Shimoyama.)
In regard to claims 8-10, Sasaki discloses all of the claimed limitations as mentioned above, except the exact arrangement as currently claimed.
Shimoyama, in fig. 24, discloses an analogous IC package (para [0038]) including leadframe with IC device CPC formed on the leads LD, die pad DP. Shimoyama further teaches the package is connected to a printed circuit board PB1 (para [0055]) in order to electrically connect the package to the board and to external devices through a conductive layer TM on the printed board; and
a printed circuit board with a principal surface that includes a mounting area on which the semiconductor device is mounted, wherein the first IC terminal and second IC terminal of the semiconductor IC, the first terminal and second terminal of the capacitor element, the first conductor and the second conductor are provided between the printed circuit board and the support region. This is common in the art.
Regarding claim 11, wherein the conductive layer is a simply connected conductive film provided at the mounting area. Fig. 24.
Regarding claim 12, the combination further discloses, wherein, in a plan view seen in the first axis direction, an outer edge of the conductive layer encompasses an outer edge of the capacitor element and encompasses the first conductor and the second conductor, and
the outer edge of the conductive layer overlaps with a portion of the semiconductor IC. Sasaki’s figs. 1 and 16.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Note: in the remarks the Applicant states that a dependent claim 3 has been added; it is actually claim 13 has been added (see the remarks’ page 6, second paragraph.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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/NATHAN W HA/Primary Examiner, Art Unit 2814