DETAILED ACTION
This office action is in response to applicant’s amendment filed on 9/19, 2025. Claims 1, 3, 6, 10-11, 16, 21-25, and 27-35 are under consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 6, 21-25, and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a dummy residue covering a lateral surface of the first redistribution structure, wherein the dummy residue comprises a semiconductor material, and the dummy residue is a residue of a dummy die which is configured to protect the waveguide from being contaminated and to be removed from the optoelectronic package during manufacturing processes.
It is unclear if the dummy residue is present in the package being claimed, or only in an intermediate device which is not the final device claimed. Alternatively, it is unclear whether claim 1 is reciting an intermediate device or the final device.
Claims 3, 6, 21-25 and 27 are dependent upon claim 1 and therefore carry the same deficiencies.
Claims 10-11, and 28-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites—a dummy residue covering the lateral surface of the encapsulant, wherein the dummy residue is a residue of a dummy die—wherein it is unclear whether claim 10 is reciting an intermediate device or the final device since the dummy die is removed to expose the dummy residue.
Claims 11 and 28-32 are dependent upon claim 10 and therefore carry the same deficiencies.
Claims 16 and 33-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites—a dummy residue in contact with a lateral surface of the encapsulant and having a material different from that of the encapsulant, wherein the dummy residue is a residue of a dummy die-- wherein it is unclear whether claim 10 is reciting an intermediate device or the final device since the dummy die is removed to expose the dummy residue.
Claims 33-34 are dependent upon claim 10 and therefore carry the same deficiencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 16, 22, and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US 2020/0091124 A1, herein “Liao”) in view of Chen et al. (US 2021/0239904 A1, herein “Chen”) in further view of Choi et al. (US 2019/0287873 A1, herein “Choi”).
Regarding claim 1, Liao discloses an optoelectronic package (Fig. 9), comprising:
a die (SOIC) having a first surface facing the photonic component comprising waveguide (320 shown in Fig. 7 and the individual SOIC units are shown in Fig. 8 where layer 300 comprises waveguide 320 therein ) and a second surface opposite the first surface;
a first redistribution structure (420) between the first surface of the die (SOIC, six system-on-integrated-circuits SoIC are shown to represent plural system-on-integrated-circuits of a semiconductor wafer [Para {0017}]) and Liao suggests the photonic component is on the first redistribution layer (420, “a predetermined optical waveguide path having one or more bent portions and one or more non-bent portions is provided” Para [0063]).
a second redistribution structure (600) in contact with the second surface of the die.
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However, Liao does not explicitly disclose “a photonic component” and “a first redistribution structure between the first surface of the die and the photonic component.”
Chen teaches an optoelectronic package with photonic component (waveguide 140), a die (200, including 210, 220, and 230) having a first surface facing the photonic component (waveguide 140).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the embedded photonic component or waveguide (140) in the interconnection structure (150) of Chen would be modifiable to the first redistribution layer (420) of Liao’s invention. Chen teaches the fabrication steps for forming the waveguides in the interconnection structure in para [0016]. One would be motivated to embed the waveguides in the interconnection structure or redistribution layer so that the waveguides are able to transmit optical signals entering from a lateral side, allowing the optoelectronic package to be “edge couplers” (Chen: Para [0016]).
Liao in view of Chen do not teach a dummy residue covering a lateral surface of the first redistribution structure, wherein the dummy residue comprises a semiconductor material, and the dummy residue is a residue of a dummy die which is configured to protect the waveguide from being contaminated and to be removed from the optoelectronic package during manufacturing processes.
Choi teaches packaging thin die wherein a dummy die 120 is added to the modular interconnect structure to prevent warpage (Para [0042]). Encapsulant (170) is disposed over the dummy units (with dummy die 120 therein). Then the encapsulant (170) and dummy die (120) is backgrinded until encapsulant 130 is reached. Grinder is able to completely remove dummy die without reaching semiconductor die (104) because encapsulant (130) provides an offset (residue) between the build-up in interconnect structure and dummy die that is greater than a thickness of semiconductor die (Para [0049]). Choi further teaches the encapsulant (130) can be completely removed or left on the side surface (Para [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize Choi uses dummy die and encapsulant as protective structure and material to prevent warpage or protect the structure side after singulation. Choi is further aware the encapsulant (residue) can be left on as a protective layer or completely removed for access to the structure behind the encapsulant. The modification of Choi to Yu in view of Chen would have been obvious since waveguide edge is known to be susceptible to damage or collecting debris during dicing. Providing a dummy die and cover the die in encapsulant to further protect the side edge or any structure as desired would have been within the knowledge and skill of a practitioner. One motivation would be to provide protection to the interior device during manufacturing process.
Claim 16. Liao discloses An optoelectronic package, comprising:
a die (SOIC) having a first surface (see annotated Fig. 16 above);
a first redistribution structure (420) disposed over the first surface of the die (SOIC);
an encapsulant encapsulating (500) the die (SOIC);
a conductive pillar (CP) penetrating the encapsulant and electrically connected to the first redistribution structure; and
a dummy residue in contact with a lateral surface of the encapsulant and having a material different from that of the encapsulant (semiconductor chip SC may be a dummy semiconductor chip such that the deposition of the a “dummy semiconductor chip” would necessarily leave “dummy residue” in contact with the lateral surface, Para [0050]).
However, Liao does not disclose a photonic component disposed over the first redistribution structure.
Chen teaches Chen teaches an optoelectronic package with photonic component (waveguide 140), a die (200, including 210, 220, and 230) having a first surface facing the photonic component (waveguide 140). See annotated Fig. 1B above.
It would have been obvious to one having ordinary skill in the art to recognize the embedded photonic component or waveguide (140) in the interconnection structure (150) of Chen would be modifiable to the first redistribution layer (420) of Liao’s invention. Chen teaches the fabrication steps for forming the waveguides in the interconnection structure in para [0016]. One would be motivated to embed the waveguides in the interconnection structure or redistribution layer so that the waveguides are able to transmit optical signals entering from a lateral side, allowing the optoelectronic package to be “edge couplers” (Chen: Para [0016]).
Liao in view of Chen do not teach a dummy residue covering a lateral surface of the first redistribution structure, wherein the dummy residue comprises a semiconductor material, and the dummy residue is a residue of a dummy die which is configured to protect the waveguide from being contaminated and to be removed from the optoelectronic package during manufacturing processes.
Liao in view of Chen do not teach a dummy residue covering a lateral surface of the first redistribution structure, wherein the dummy residue comprises a semiconductor material, and the dummy residue is a residue of a dummy die which is configured to protect the waveguide from being contaminated and to be removed from the optoelectronic package during manufacturing processes.
Choi teaches packaging thin die wherein a dummy die 120 is added to the modular interconnect structure to prevent warpage (Para [0042]). Encapsulant (170) is disposed over the dummy units (with dummy die 120 therein). Then the encapsulant (170) and dummy die (120) is backgrinded until encapsulant 130 is reached. Grinder is able to completely remove dummy die without reaching semiconductor die (104) because encapsulant (130) provides an offset (residue) between the build-up in interconnect structure and dummy die that is greater than a thickness of semiconductor die (Para [0049]). Choi further teaches the encapsulant (130) can be completely removed or left on the side surface (Para [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize Choi uses dummy die and encapsulant as protective structure and material to prevent warpage or protect the structure side after singulation. Choi is further aware the encapsulant (residue) can be left on as a protective layer or completely removed for access to the structure behind the encapsulant. The modification of Choi to Yu in view of Chen would have been obvious since waveguide edge is known to be susceptible to damage or collecting debris during dicing. Providing a dummy die and cover the die in encapsulant to further protect the side edge or any structure as desired would have been within the knowledge and skill of a practitioner. One motivation would be to provide protection to the interior device during manufacturing process.
Claim 22. The optoelectronic package of claim 1, wherein a cross-sectional view, the first redistribution structure has a first side and a second side opposite to the first side, the second redistribution structure has a third side and a fourth side opposite to the third side is substantially aligned with the first side, and the fourth side is misaligned with the second side (see wiring edges in 624 are not aligned with 424 in Fig. 16).
Claim 33. The optoelectronic package of claim 16, wherein the dummy residue is disposed on a surface, exposed by the encapsulant, of the first redistribution structure (“dummy semiconductor chip” at SC, see Para [0050]).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Chen.
Regarding claim 34, Liao discloses the invention of claim 16, Liao further discloses in Fig. 21 a second redistribution structure (600) spaced apart from the first redistribution structure (420) by the encapsulant (500’); a solder element (424, 624) on the second redistribution structure; and a circuit board (semiconductor device 70 implicitly has a circuit board) disposed on the solder element, wherein the circuit board is electrically connected to the photonic component through the solder element (and bond pads 720), the second redistribution structure, the conductive pillar, and the first redistribution structure in sequence, and the first redistribution structure contacts the encapsulant and the photonic component (Fig. 21).
Claims 10-11, 28-32 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Chang et al. (US 9,939,578 B2, herein “Chang”) in further view of Choi.
Claim 10. Liao discloses an optoelectronic package (Fig. 9), comprising:
a die (SOIC) disposed over the active surface of the photonic component;
a first redistribution structure (420) disposed between the die (SOIC) and the photonic component (410); and
an encapsulant encapsulating (500) the die, wherein a lateral surface of the encapsulant is noncoplanar with the lateral surface of the first redistribution structure (500’ only covers area without SOIC, thus in those area it is considered non-coplanar with 420, see Fig. 17).
However, Liao does not disclose a photonic component having a recess region on an active surface of the photonic component and a waveguide, wherein a lateral surface of the waveguide is exposed from the recess region.
Chang teaches a photonic component (100) having a recess region (not labeled, right side of arrow D4 in Fig. 2A, at label 110A) on an active surface of the photonic component (100) and a waveguide (110A), wherein a lateral surface of the waveguide is exposed from the recess region.
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It would have been obvious to one having ordinary skill in the art to recognize the recessed region in the photonic component of Chang can be modified to the redistribution substrate of Liao’s invention to provide an optical coupling of the input waveguide to the planar waveguide of substrate. The motivation for modifying the redistribution layer with a recess as shown by Chang is providing a cost effective method of edge coupling devices such as laser to the substrate without the costly step of active alignment between the input device and the substrate (Chang: Abstract and Col. 1, lines 48-51).
Liao in view of Chang do not teach a dummy residue covering a lateral surface of the first redistribution structure, wherein the dummy residue comprises a semiconductor material, and the dummy residue is a residue of a dummy die which is configured to protect the waveguide from being contaminated and to be removed from the optoelectronic package during manufacturing processes.
Choi teaches packaging thin die wherein a dummy die 120 is added to the modular interconnect structure to prevent warpage (Para [0042]). Encapsulant (170) is disposed over the dummy units (with dummy die 120 therein). Then the encapsulant (170) and dummy die (120) is backgrinded until encapsulant 130 is reached. Grinder is able to completely remove dummy die without reaching semiconductor die (104) because encapsulant (130) provides an offset (residue) between the build-up in interconnect structure and dummy die that is greater than a thickness of semiconductor die (Para [0049]). Choi further teaches the encapsulant (130) can be completely removed or left on the side surface (Para [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize Choi uses dummy die and encapsulant as protective structure and material to prevent warpage or protect the structure side after singulation. Choi is further aware the encapsulant (residue) can be left on as a protective layer or completely removed for access to the structure behind the encapsulant. The modification of Choi to Yu in view of Chen would have been obvious since waveguide edge is known to be susceptible to damage or collecting debris during dicing. Providing a dummy die and cover the die in encapsulant to further protect the side edge or any structure as desired would have been within the knowledge and skill of a practitioner. One motivation would be to provide protection to the interior device during manufacturing process.
Claim 11. The optoelectronic package of claim 10, further comprising: a second redistribution structure (600) spaced apart from the first redistribution structure (420) by the encapsulation (500).
Claim 28. Liao in view of Chang in further view of Choi teach the waveguide is configured to transmit or receive an optical signal through the lateral surface of the waveguide (See Fig. 2A of Chang).
Claim 29. The optoelectronic package of claim 10, wherein the recess region is recessed from the active surface of the photonic component toward a backside surface of the photonic component (Chang: Fig. 2A). The examiner considers Chang’s substrate (101) forms the “backside surface of the photonic component”.
Claim 30. Liao in view of Chang in further view of Choi teach claim 11, wherein the lateral surface of the encapsulant (500) is substantially aligned with a lateral surface of the second redistribution structure (420).
Claim 31. Liao in view of Chang in further view of Choi teach claim 11, wherein a width of the encapsulant (500) is substantially equal to a width of the second redistribution structure (600).
Claim 32. Liao in view of Chang in further view of Choi teach claim 11, wherein the photonic component has an upper surface exposed by recess region, and the upper surface is non-coplanar with the active surface of the photonic component (Fig. 9C-9D show tapering edges of the waveguide which are necessarily non-coplanar with the active surface of the photonic component).
Claim 35. Liao in view of Chang in further view of Choi teach claim 10, wherein the first redistribution structure comprises an interconnection structure (424) and a dielectric layer encapsulating the interconnection structure (422), the encapsulant encapsulates the die and contacts an upper surface of the dielectric layer of the first redistribution structure
In another embodiment shown in Fig. 29, the encapsulant is provided at an outer lateral surface of the encapsulant is recessed (above IM2) from an outer lateral surface of the dielectric layer of the first redistribution structure, and the outer lateral surface of the encapsulant is spaced apart from the die. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the recess is provided for access between the package and the external device such as a side coupler. One would be motivated to provide a side coupler such as a waveguide to input or output an optical signal from the photonic device within the package.
Claims 3, 6, 21, 23-25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Chen in further view of Choi as applied to claim 1 above, and further in view of Yu et al. (US 10,867,982 B2, herein “Yu”).
Claims 3 and 21. Liao in view of Chen in further view of Choi disclose the invention of claim 1, but Liao in view of Chen do not disclose a solder element disposed between the first surface of the die and the first redistribution structure, wherein the solder element comprises an alloy of tin.
Yu teaches an optoelectronic package wherein conductive connectors (258) are solder balls are alloy of tin (Col. 11, lines 13-18) used to solder die (118) to redistribution layer (104) (Col. 11, lines 33-45). The connection of the die and the redistribution layer using solder balls would necessarily aligns the die to vertically overlaps the solder balls.
It would have been obvious to one having ordinary skill in the art to recognize the solder in Yu would be compatible to the optoelectronic package of Liao, since both Yu and Liao are in the same field of endeavor. One would be motivated to use conductive solders to create stronger bonds and electrical connections.
Claim 6. Liao in view of Chen in further view of Choi disclose the invention of claim 1, and Liao teaches the encapsulant material is provided between the die (SoIC).
However, Liao in view of Chen in further view of Choi do not teach an encapsulant, wherein the die is embedded in the encapsulant and the encapsulant covers the first surface of the die.
Yu teaches the logic die (118) is surrounded by an encapsulant (126) and the encapsulant also formed over the redistribution structure (122). The formation of the encapsulant over the redistribution structure (122) implies that the encapsulant is provided below the logic die (118) or in other words, the logic die (118) is embedded in the encapsulant (Yu: Fig. 2, Col. 3, lines 29-60).
It would have been obvious to one having ordinary skill in the art to recognize embedding the logic die in encapsulant, as disclosed by Yu, would be modifiable to the die (SoIC) in the package structure in Fig. 16 of Liao, as Yu, Liao, and Choi are in the same field of endeavor. One would be motivated to embed the logic die in the encapsulant to create electrical isolations between the electrical components reduces electrical stress which causes failures in the electrical components.
Claim 24. The optoelectronic package of claim 6, wherein the encapsulant has a lateral surface substantially aligned with a lateral surface of the second redistribution structure (see Yu: Fig. 17 the edge of each layer).
Claim 25. The optoelectronic package of claim 6, further comprising: Choi teaches wherein dummy residue (encapsulant that is backgrinded, examiner considers the dust from backgrinding) covers the lateral surface of the encapsulant (Choi: Para [0050]).
Claim 27, Liao discloses the invention of claim 25, but Liao in view Chen in further view of Choi and in further view of Yu is silent to the dummy residue has a roughness greater than a roughness of a lateral surface of the second redistribution structure.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to optimize the residue roughness range to increase bonding, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Claim 23. Liao in view of Chen in further view of Choi tech the invention of claim 22, however, Liao in view of Chen do not teach a portion of the first redistribution structure is free from vertically overlapping the second redistribution structure.
Yu teaches using solder balls to couple the die with the redistribution structure. But Yu is silent to the first redistribution structure is free from vertically overlapping the second redistribution structure.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the two redistribution structures may have slight right shift or left shift to improve alignment of the structure in between. Due to the shifting portion, the two redistribution structure won’t overlap. The benefits of this modification include providing shifting eases to align structures between the two redistribution structures.
Response to Arguments
Applicant’s arguments with respect to claims 1, 6, 10,-11, 16, 21-25, and 27-34 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached on (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874