Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: the claim repeats the subject matter “wherein the first to fourth channel structures of the first column of channel structures are spaced apart from each other in the first direction”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
Claim(s) 1-9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (PGPub No. 20210366825) in further view of Mizutani (US Patent No. 9929174) and Lee (PGPub No. 20160322376).
Regarding claim 1, Shin teaches a semiconductor memory device comprising: a source structure having a surface extending in a first direction and a second direction different from the first direction (Fig. 2 points to a circuit diagram of a memory block (memory device) comprising a common source line CSL (source structure).); a first drain select line spaced apart from the source structure in a third direction, the third direction crossing the surface of the source structure (Id. points to a string select line SSL1 (first drain select line).); a first group of bit lines including first, second, third, and fourth bit lines, wherein the first group of bit lines is spaced apart from the first drain select line in the third direction, wherein the first to fourth bit lines of the first group of bit lines extend in the first direction, and wherein the first to fourth bit lines of the first group of bit lines are spaced apart from each other in the second direction (Figs. 2 and 3 point to a plurality of bit lines BL (first group of bit lines) comprising bit lines B1 (first bit line), B2 (second bit line), B3 (third bit line), and B4 (fourth bit line).); a first column of channel structures including first, second, third, and fourth channel structures, wherein the first to fourth channel structures of the first column of channel structures are spaced apart from each other in the first direction, (Fig. 3 points to a first layout/arrangement structure CG1 (first column of channel structures) comprising channel structures C1 (first channel structure), C2 (second channel structure), C3 (third channel structure), and C4 (fourth channel structure).); a first contact group of contact plugs including first, second, third, and fourth contact plugs, wherein the first to fourth contact plugs of the first contact group of contact plugs connect the first to fourth channel structures of the first column of channel structures to the first to fourth bit lines of the first group of bit lines, respectively (Id. points to the channel structures C1-C4 (first to fourth channel structures) each comprising a contact CNT (first to fourth contact plugs).); and a word line disposed between the first drain select line and the source structure and surrounding the first to fourth channel structures of the first column of channel structures (Fig. 2 points to a word line WL1.), wherein each of the first to fourth channel structures of the first column of channel structures extend in the second direction to overlap the first to fourth bit lines of the first group of bit lines (Fig. 3 points to a first layout/arrangement structure CG1 (first to fourth channel structures) and bit lines BL1-BL4 (first to fourth bit lines). [0049] further points to some example embodiments where two or more bit lines may be arranged to overlap one channel structure; it is interpreted as obvious to one of ordinary skill in the art would at least attempt to overlap all four bit lines over one channel structure.).
Shin fails to teach wherein the first drain select line is spaced apart from another drain select line with an insulating structure interposed therebetween, and wherein the insulating structure extends in the second direction; wherein the first to fourth channel structures of the first column of channel structures are spaced apart from each other in the first direction and are arranged substantially at a same level in a second direction, and wherein the first to fourth channel structures of the first column of channel structures, each extend from the source structure in the third direction to pass through the first drain select line.
Mizutani teaches wherein the first drain select line is spaced apart from another drain select line with an insulating structure interposed therebetween, and wherein the insulating structure extends in the second direction (Figs. 13A-13B and 17A-17B point to embodiments of a memory device comprising drain select level isolation structures 72.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Shin and Mizutani, such that each drain select line is spaced apart and separated from each other by an insulating structure in order to reduce interference by improving electrical isolation.
Shin et al. fails to teach wherein the first to fourth channel structures of the first column of channel structures are spaced apart from each other in the first direction and are arranged substantially at a same level in a second direction, and wherein the first to fourth channel structures of the first column of channel structures, each extend from the source structure in the third direction to pass through the first drain select line.
Lee teaches wherein the first to fourth channel structures of the first column of channel structures are spaced apart from each other in the first direction and are arranged substantially at a same level in a second direction, and wherein the first to fourth channel structures of the first column of channel structures, each extend from the source structure in the third direction to pass through the first drain select line (Fig. 3 points to a memory cell array 110 comprising four vertical channel layers VC (first to fourth channel structures) which extend from a source line CSL (source structure) and pass through a drain select line DSL.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shin et al. and Lee, such that the first to fourth channel structures are arranged substantially at a same level and pass through the first drain select line in order to create a matrix form that simplifies the fabrication process and/or allows for easier routing.
Regarding claim 2, Shin teaches a second column of channel structures including first, second, third, and fourth channel structures (Fig. 3 points to a second layout/arrangement structure CG2 (second column of channel structures) comprising channel structures C1 (first channel structure), C2 (second channel structure), C3 (third channel structure), and C4 (fourth channel structure).), wherein the first to fourth channel structures of the second column of channel structures are disposed at a position displaced in a diagonal direction with respect to the first to fourth bit lines of the first group of bit lines from the first to fourth channel structures of the first column of channel structures (Fig. 4 and [0057] point to a memory cell array 100 comprising a plurality of sub-arrays partitioned by a plurality of word line cuts, such that a first array SA1 (first column of channel structures) may be connected to first to fourth bit lines BL1 to BL4 (first group of bit lines), while an additional sub-array (second column of channel structures) may be connected to other bit lines BL5 to BLj. Fig. 4 and [0059] further points to the first sub-array SA1 and the second sub-array SA2 comprising different arrangement structures (column of channel structures); it is considered obvious that one of ordinary skill in the art would also apply this to the rest of the plurality of sub-arrays.); a second group of bit lines including first, second, third, and fourth bit lines, wherein the first to fourth bit lines of the second group of bit lines overlap each of the first to fourth channel structures of the second column of channel structures, wherein the first to fourth bit lines of the second group of bit lines extend in the first direction, and wherein the first to fourth bit lines of the second group of bit lines are spaced apart from each other in the second direction (Fig. 4 and [0057] point to at least one additional sub-array (second column of channel structures) connected to other bit lines BL5 to BLj (second group of bit lines; first, second, third, and fourth bit lines).); and a second contact group of contact plugs including first, second, third, and fourth contact plugs, wherein the first to fourth contact plugs of the second contact group of contact plugs connect the first to fourth channel structures of the second column of channel structures to the first to fourth bit lines of the second group of bit lines, respectively (Fig. 3 points to the channel structures C1-C4 (first to fourth channel structures) each comprising a contact CNT (first to fourth contact plugs).).
Shin fails to teach wherein the first to fourth channel structures of the second column of channel structures each extend in the third direction from the source structure to pass through the first drain select line.
Lee teaches wherein the first to fourth channel structures of the second column of channel structures each extend in the third direction from the source structure to pass through the first drain select line (Fig. 3 points to a memory cell array 110 comprising four vertical channel layers VC (first to fourth channel structures) which extend from a source line CSL (source structure) and pass through a drain select line DSL.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shin et al. and Lee, such that the first to fourth channel structures are arranged substantially at a same level and pass through the first drain select line in order to create a matrix form that simplifies the fabrication process and/or allows for easier routing.
Regarding claim 3, Shin teaches wherein the first to fourth channel structures of the first column of channel structures are spaced apart from the first to fourth channel structures of the second column of channel structures in the second direction (Fig. 4 points to a plurality of sub-arrays arranged such that at least one sub-array (first column of channel structures) is connected to bit lines BL1-BL4, and an additional sub-array (second column of channel structures) is connected to bit lines BL5-BLj.).
Regarding claim 4, Shin teaches wherein the first to fourth bit lines of the first group of bit lines do not overlap the first to fourth channel structures of the second column of channel structures, and the first to fourth bit lines of the second group of bit lines do not overlap the first to fourth channel structures of the first column of channel structures (Fig. 4 points to a plurality of sub-arrays arranged such that at least one sub-array (first column of channel structures) is connected to bit lines BL1-BL4, and an additional sub-array (second column of channel structures) is connected to bit lines BL5-BLj.).
Regarding claim 5, Shin teaches a second drain select line spaced apart from the first drain select line in the first direction (Fig. 2 points to string select line SSL2 (drain select line).); fifth, sixth, seventh, and eighth channel structures of the first column of channel structures adjacent to the first to fourth channel structures of the first column of channel structures in the first direction (Fig. 5 points to sub-array SA1 (first column of channel structures) further comprising a second channel group CA2 (fifth, sixth, seventh, and eighth channel structures).); and fifth, sixth, seventh, and eighth contact plugs of the first contact group of contact plugs connecting the fifth to eighth channel structures of the first column of channel structures to the first to fourth bit lines of the first group of bit lines, respectively (Figs. 3 and 5 point to the second channel group CA2 (fifth to eight channel structures) comprising a plurality of contacts CNT (fifth, sixth, seventh, and eighth contact plugs).).
Shin fails to teach the fifth to eighth channel structures of the first column of channel structures each extending from the source structure in the third direction to pass through the second drain select line.
Lee teaches the fifth to eighth channel structures of the first column of channel structures each extending from the source structure in the third direction to pass through the second drain select line (Fig. 3 points to a memory cell array 110 comprising four vertical channel layers VC (fifth to eighth channel structures) which extend from a source line CSL (source structure) and pass through a drain select line DSL.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shin et al. and Lee, such that the fifth to eighth channel structures are arranged substantially at a same level and pass through the second drain select line in order to create a matrix form that simplifies the fabrication process and/or allows for easier routing.
Regarding claim 6, Shin teaches wherein the word line continuously extends in the first direction to surround fifth to eighth channel structures of the first column of channel structures (Fig. 2 points to word line WL1.).
Regarding claim 7, Shin in combination with Mizutani teaches the insulating structure disposed between the first drain select line and the second drain select line (Figs. 13A-13B and 17A-17B of Mizutani point to drain select level isolation structures 72. Fig. 5 of Shin points to a first select line cut region SSLC1 (insulating structure).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shin et al. and Mizutani, such that the insulating structure is disposed between the first drain select line and the second drain select line in order to reduce interference by improving electrical isolation.
Regarding claim 8, Shin teaches wherein the fourth channel structure of the first column of channel structures and the fifth channel structure of the first column of channel structures are adjacent to each other with the insulating structure interposed therebetween, the fifth channel structure of the first column of channel structures is spaced apart from the insulating structure in the first direction (Fig. 5 points to the bottommost channel structure CS of the first group CA1 (fourth channel structure), the topmost channel structure CS of the second group CA2 (fifth channel structure), and the first select line cut region SSLC1 (insulating structure).), and the fourth channel structure of the first column of channel structures includes a first area overlapping the insulating structure and a second area extending from the first area in a direction away from the fifth channel structure of the first column of channel structures ([0066] points to how in some example embodiments (emphasis added), the channel structures CS may not be formed in the first select line cut region SSLC1 (insulating structure). This is interpreted to also teach that in other example embodiments, at least one channel structure (fourth channel structure) may be formed in the first select line cut region SSLC1 (insulating structure).).
Regarding claim 9, Shin teaches wherein the fourth channel structure of the first column of channel structures is formed shorter than the second area in the first area in the third direction, and the fourth channel structure of the first column of channel structures extends in the third direction along a sidewall of the insulating structure in the second area (Fig. 5 points to the bottommost channel structure of CA1 (fourth channel structure). The disclosure does not appear to lend any criticality or significance to the exact lengths of the first and second areas comprising the fourth channel structure and, as such, is deemed a matter of choice that a person of ordinary skill in the art would have found obvious. Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).).
Regarding claim 16, Lee teaches wherein the first drain select line continuously extends in the second direction across the first to fourth channel structures of the first column of channel structures, and wherein each of the first to fourth channel structures passes through the same first drain select line without being separated by the insulating structure in the second direction (Fig. 3 points to a memory cell array 110 comprising four vertical channel layers VC (first to fourth channel structures) which pass through a drain select line DSL.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Shin et al. and Lee, such that the first drain select line continuously extends across the first to fourth channel structures in order to create a matrix form that simplifies the fabrication process and/or allows for easier routing.
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/11/2026, with respect to the rejection(s) of claims 1-9 and 16 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made over Shin et al. in further view of Lee (PGPub No. 20160322376).
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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