Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 09/21/22. Claims 1-33 are pending in this application.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-15, 17-20, 22, and 23 are rejected under 35 U.S.C. §102(a)(1)(2) as being unpatentable over Ramaswamy (US20190006376).
Regarding claim 1, Ramaswamy, at least at fig 10, discloses a memory device, comprising: a first horizontally oriented access device (see fig 10) having a first source/drain region and a second source/drain region separated by a first channel region (see fig 10, left 20/22 being separated by 24), the first access device being operatively controlled by a first gate (see 26 on the left being the first gate, see fig 10); and a second horizontally oriented access device having a first source/drain region and a second source/drain region separated by a second channel region(see fig 10, right 20/22), the second access device being operatively controlled by a second gate(see 26 on the right being the second gate, see fig 10); and a shared storage node coupled between the second source/drain regions of the first access device and the second access device (see capacitor 48b, 52b separating left and right devices).
Regarding claim 2, Ramaswamy at least at fig 10 discloses the memory device of claim 1, wherein the first and the second gates are electrically connected (see fig 10 where the first and second gates are connected via the capacitor, 52b).
Regarding claim 3, Ramaswamy discloses the memory device of claim 1, wherein the first and the second gates are vertically oriented gates (see fig 10 disclosing vertically oriented gates).
Regarding claim 5, Ramaswamy discloses the memory device of claim 1, wherein the first and the second gates are horizontally oriented gates (see fig 10 disclosing horizontal gates).
Regarding claim 7, Ramaswamy discloses the memory device of claim 1, wherein the shared storage node comprises a first electrode coupled to the second source/drain region of the first access device and a second electrode coupled to the second source/drain region of the second access device (see storage node capacitor in fig 10 is shared between two transistors).
Regarding claim 8, Ramaswamy discloses the memory device of claim 1, wherein the first and the second access devices are thin film transistors (TFTs) and the shared storage node is a horizontally oriented capacitor (see para [0005] disclosing thin insulating film).
Regarding claim 9, Ramaswamy discloses the memory device of claim 1, wherein the first and the second access devices are thin film transistors (TFTs) and the shared storage node is a ferroelectric storage node (see para [0006] disclosing FeFet).
Regarding claim 10, Ramaswamy discloses the memory device of claim 1, wherein the memory device comprises a vertically oriented three-dimensional (3D), multi-tiered memory array with each tier having two transistor, one capacitor (2T1C) memory cells (see fig 10, disclosing 2 transistors 1 capacitor).
Regarding claim 11, Ramaswamy, at least at fig 10 discloses a memory device (see para [0048]), comprising: a first horizontally oriented access device having a first source/drain region (see left 20/22) and a second source/drain region (20/22 )separated by a first channel region(see fig 10, 24), the first access device being operatively controlled by a first gate(see 26 on the left being the first gate, see fig 10); and a second horizontally oriented access device having a first source/drain region and a second source/drain region (20/22) separated by a second channel region(see fig 10, right 20/22), the second access device also being operatively controlled by a second gate (see 26 on the right being the second gate, see fig 10); and a storage node (see capacitor 52b) comprising: a first electrode (left 56b)coupled to the second source/drain region (20) of the first access device (see left 50b); and a second electrode coupled to the second source/drain region of the second access device (see right 50b, connected to 20 fig 10).
Regarding claim 12, Ramaswamy discloses the memory device of claim 11, wherein the first and the second gates are gate on two side (G2S) structures on opposing sides, respectively, of the first and the second channel regions (see fig 10 disclosing two gate structures on opposing horizontal sides).
Regarding claim 13, Ramaswamy discloses the memory device of claim 11, wherein the first gate and the second gate are electrically coupled together (see fig 10 where the gates are commonly/electrically connected via the capacitor).
Regarding claim 14, Ramaswamy discloses the memory device of claim 11, wherein the first and the second horizontally oriented access devices are thin film transistors (TFTs) and the shared storage node is a horizontally oriented capacitor located in a same horizontal tier to form a two transistor, one capacitor (2T1C) memory cell(see para [0005] disclosing thin insulating film).
Regarding claim 15, Ramaswamy discloses the memory device of claim 14, wherein the memory device comprises a vertically oriented three-dimensional (3D), multi-tiered memory array with each tier having two transistor, one capacitor (2T1C) memory cells(see fig 10, disclosing 2 transistors 1 capacitor).
Regarding claim 17, Ramaswamy discloses the memory device of claim 11, wherein the storage node is a shared storage node located in a same plane, horizontally between the first access device and the second access device (see fig 10, disclosing capacitor and electrodes 50b are floating on each side).
Regarding claim 18, Ramaswamy discloses the memory device of claim 17, wherein the shared storage node is a capacitor and both electrodes of the capacitor are floating electrodes(see fig 10, disclosing capacitor and electrodes 50b are floating on each side).
Regarding claim 19, Ramaswamy discloses the memory device of claim 11, wherein the storage node is a horizontally oriented, ferroelectric storage node located between the first access device and the second access device (see fig 10 disclosing storage note horizontally oriented between two transistors).
Regarding claim 20, Ramaswamy discloses a memory device, comprising: an array of vertically stacked two transistor, one capacitor (2T1C) memory cells (see fig 10), the 2T1C memory cells, comprising: a first horizontally oriented transistor having a first source/drain region and a second source/drain region separated by a first channel(see fig 10, left 20/21), the first horizontally oriented transistor being operatively controlled by a first vertically oriented gate(see 26 on the left being the first gate, see fig 10); a second horizontally oriented transistor having a first source/drain region and a second source/drain region separated by a second channel(see fig 10, left 20/21), the second horizontally oriented transistor being operatively controlled by a second vertically oriented gate(see 26 on the right being the second gate, see fig 10); and a floating capacitor coupled to the second source drain regions 20/21 of the first and the second horizontally oriented transistors(see capacitor 52b); a first horizontally oriented digit line coupled to the first source/drain region of the first horizontally oriented transistor (see fig 10, element 57, left); and a second horizontally oriented digit line coupled to the first source/drain region of the second horizontally oriented transistor(see fig 10, element 57, right).
Regarding claim 22, Ramaswamy discloses the memory device of claim 20, wherein the floating capacitor comprises: a first electrode coupled to the second source/drain region of the first horizontally oriented transistor; and a second electrode coupled to the second source/drain region of the second horizontally oriented transistor (see fig 10 disclosing two horizontal transistors coupled with a center capacitor).
Regarding claim 23, Ramaswamy discloses the memory device of claim 20, wherein the first and the second horizontally oriented transistors are thin film transistors (TFTs) (see para [0005] disclosing thin insulating film).
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 6, 16, and 21 are rejected under 35 U.S.C.§103 as being unpatentable over Ramaswamy and further in view of Juengling (US 20180182761 A1).
Regarding claim 4, Ramaswamy discloses the memory device of claim 3, wherein the first source/drain region of the first horizontally oriented access device and the first source/drain region of the second horizontally oriented access device are coupled to a complimentary pair of horizontally oriented digit lines
However, Ramaswamy does not disclose electrically connected to a sense amplifier. However, Juengling discloses a connection of a memory device to a sense amplifier. Ramaswamy and Juengling are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Ramaswamy with Juengling. Ramaswamy and Juengling may be combined by, for example, completing Ramaswamy’s memory device with a sense amplification, as taught in Juengling. One having ordinary skill in the art would have been motivated to combine Ramaswamy with Juengling in order, to, for example, to be an operable memory device, see paras [0032] and [0033].
Regarding claim 6, Ramaswamy discloses the memory device of claim 5, wherein the first source/drain region of the first horizontally oriented access device and the first source/drain region of the second horizontally oriented access device are coupled (see fig 10 disclosing two horizontally oriented transistors) to a complimentary pair of vertically oriented digit lines (see fig 10).
However, Ramaswamy does not disclose digit lines electrically connected to a sense amplifier. However, Juengling discloses a connection of a memory device to a sense amplifier. Ramaswamy and Juengling are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Ramaswamy with Juengling. Ramaswamy and Juengling may be combined by, for example, completing Ramaswamy’s memory device with a sense amplification, as taught in Juengling. One having ordinary skill in the art would have been motivated to combine Ramaswamy with Juengling in order, to, for example, to be an operable memory device, see paras [0032] and [0033].
Regarding claim 16, Ramaswamy discloses the memory device of claim 11, wherein the first source/drain region of the first horizontally oriented access device and the first source/drain region of the second horizontally oriented access device are coupled to a complimentary pair of horizontally oriented digit lines electrically.
However, Ramaswamy does not disclose digit lines electrically connected to a sense amplifier. However, Juengling discloses a connection of a memory device to a sense amplifier. Ramaswamy and Juengling are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Ramaswamy with Juengling. Ramaswamy and Juengling may be combined by, for example, completing Ramaswamy’s memory device with a sense amplification, as taught in Juengling. One having ordinary skill in the art would have been motivated to combine Ramaswamy with Juengling in order, to, for example, to be an operable memory device, see paras [0032] and [0033].
Regarding claim 21, Ramaswamy discloses the memory device of claim 20, wherein the first and the second horizontally oriented digit lines are complementary digit lines (see fig 10).
However, Ramaswamy does not disclose digit lines electrically connected to a sense amplifier. However, Juengling discloses a connection of a memory device to a sense amplifier. Ramaswamy and Juengling are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Ramaswamy with Juengling. Ramaswamy and Juengling may be combined by, for example, completing Ramaswamy’s memory device with a sense amplification, as taught in Juengling. One having ordinary skill in the art would have been motivated to combine Ramaswamy with Juengling in order, to, for example, to be an operable memory device, see paras [0032] and [0033].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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