CTFR 17/949,817 CTFR 78931 8/DETAILED ACTION Claims 1-22 are pending in this application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claims 1, 3-7, an d 13 are reject ed under 35 U.S.C. 103 as being unpatentable over U.S. Pub. N o. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2020/0358721 A1 to Rimmer et al. (hereinafter referred to as Rimmer’721) and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al. As to cl aim 1, Memon teaches a device, comprising: a network interconnect ( “…The request for the coprocessor resource (in particular, here, memory) is transmitted from the client/application side, over the network, to the functional coprocessor/server side of FIG. 5 …” paragraph 0052); a first processing unit ( Host CPU(s) 210 ) to perform application-level processing tasks ( applications) (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory…” paragraph 0020); and a second processing unit ( one or more coprocessors CP1, CP2, CP3, . . . , CPn, of which graphics processing units (GPUs)) in communication with the first processing unit via the network interconnect, wherein the first processing unit is to offload at least one of computation tasks and communication tasks to the second processing unit (“… Depending on the configuration, the hardware platform 200 may also include one or more coprocessors CP1, CP2, CP3, . . . , CPn, of which graphics processing units (GPUs) are one of many examples; these may, however, also be located within other systems, accessible via any standard buses or networks, such that the concept of “hardware platform” may be broadened to include such “peripheral” or even remote coprocessors, such as coprocessors in cloud computing environments. Embodiments may also be used in other forms of distributed systems, such as a software-defined infrastructure (SDI). The applications 100 may also be running in a distributed processing environment, with more than one server handling processing tasks…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory …” paragraphs 0019/0020) while the first processing unit performs the application-level processing tasks, and wherein the second processing unit is to provide a result to the first processing unit when the at least one of computation tasks and communication tasks are completed (“.. 8) The request results are then returned to the application/client side via the network…9) The request is then mapped back to the ID of the originally requested device…After completion of execution of the kernel, the device results may be copied back to the calling host, after which the device may be deallocated and, for example, made available for use in a subsequent call ...” paragraphs 0057-0058/0062). Memon is silent with reference to a result vector and wherein the first processing unit is further to send a control message to the second processing unit to initialize the second processing unit and initiate a reduction operation by pre-allocating a buffer contained in memory of the second processing unit and wherein the first processing unit is to offload a computation task comprising a reduction operation. Rimmer’721 teaches a network interconnect result vector ( construct a result vector) (“… Message Passing Interface (MPI) is a communication protocol used for programming computers for parallel computing. AllReduce is an existing MPI function which can be implemented as a sequence of point-to-point sends and receives. The AllReduce operation can take a vector of data from each participant, apply a function across each element of the vector (e.g., sum, addition, average, minimum, or maximum) and construct a result vector which is distributed to the participants. AllReduce is implemented in a variety of other popular APIs, such as Uber's Horovod, nVidia's NCCL, Intel's MLSL, and so forth. These implementations and algorithms are similar or identical to those used inside various MPI implementations…” paragraphs 0022/0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon with the teaching of Rimmer’721 because the teaching of Rimmer‘721 would improve the system of Memon by providing a technique for providing a computed result to a requester. Klenk teaches and wherein the first processing unit is further to send a control message to the second processing unit to initialize the second processing unit ( In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 300) and initiate a reduction operation by pre-allocating a buffer contained in memory of the second processing unit ( For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302) (“… In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 300 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU 300. For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 300. The front end unit 315 receives pointers to one or more command streams. The front end unit 315 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 300 .…” paragraph 0066) and wherein the first processing unit is to offload a computation task comprising a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing. As to claim 3, Memon teaches the device of claim 1, wherein the first processing unit comprises a primary processor (( Host CPU(s) 210 ) and wherein the second processing unit comprises a network-attached co-processor ( one or more coprocessors CP1, CP2, CP3, . . . , CPn, of which graphics processing units (GPUs)) . As to claim 4, Memon teaches the device of claim 3, wherein the primary processor comprises a Central Processing Unit (CPU) that utilizes a CPU memory as part of performing the application-level processing tasks and wherein the network-attached co-processor comprises a Data Processing Unit (DPU) that utilizes a DPU memory as part of performing the at least one of computation tasks and communications tasks ( coprocessor device memory) (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory …” paragraph 0020). a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing. As to claim 5, Memon teaches the device of claim 4, wherein the DPU is to receive the control message from the CPU and in response thereto allocate at least one buffer from the DPU memory to perform the at least one of computation tasks and communication tasks (“…In the figures, the component 700 —the coordinator—is shown as being separate from the MVL instances. This will often be efficient, since this component may then act as a supervisory component that may operate even to create MVL instances. It would also be possible, however, to include the coordination function in components within the MVL instances themselves, and to choose a “victim” coprocessor using a polling procedure. For example, if MVL-1 needs 10 GB to handle a call from application 100-1, but the coprocessor it has called has only 5 GB available, then MVL-1 could broadcast a message to all other current MVL instances to request allocation of one of their coprocessor memories. For example, the MVL instance of a currently idle coprocessor could signal back to MVL-1 that it is able to temporarily relinquish use of its coprocessor memory. If more than one signal back availability, then MVL-1 could choose the one most local, or that has the memory that would cause the least overhead, etc …” paragraph 0070). a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing. As to claim 6, Rimmer’721 teaches the device of claim 4, wherein the DPU is to perform the at least one of computation tasks and communication tasks as part of an Allreduce collective operation ( AllReduce computation ) (“… FIG. 4B shows an example operation in an AllReduce computation. The MPI Collective can be implemented as a sequence of point-to-point MPI_Send and MPI_Recv calls (e.g., MPI Two Sided communications) to copy vectors to a participant. The receiver MPI Collective performs a selected operation (e.g., sum) to accumulate the final result vector. More specifically, in this example, two participants (e.g., a sender and a receiver) use MPI_Send and MPI_Recv to transfer a vector of data using an eager mechanism. As the individual eager packets arrive, the receiver NIC places content of the packets into an intermediate bounce buffer. The NIC software and/or hardware examines the packet, performs tag matching, and then copies the data into the buffer supplied by the MPI Collective as part of the MPI_Recv call. Once the MPI_Recv is complete, the receiver combines the data in the temporary buffer with its ongoing computation result (e.g., Compute Collective). The receiver and sender can repeat the sequence, with a different pairing of participants …” paragraph 0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Klenk with the teaching of Rimmer’721 because the teaching of Rimmer‘721 would improve the system of Memon and Klenk by providing a technique for providing a computed result to a requester. a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing. As to clam 7, Memon teaches the device of claim 4, wherein the CPU memory and the DPU memory are to register with the network interconnect before communications between the CPU and DPU are enabled via the network interconnect ( over the network) (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory…3) The request for the coprocessor resource (in particular, here, memory) is transmitted from the client/application side, over the network, to the functional coprocessor/server side of FIG. 5 …” paragraphs 0020/0052). As to claim 13, Rimmer’721 teaches the device of claim 1, wherein the application-level processing tasks ( AllReduce) (“… For example, as part of an execution of AllReduce using parallel computation, to perform sharing of vectors with two or more other platforms, application 604 executing on host system 602 can utilize processor executed MPI layer 606 and any of platforms 670-0 to 670-N can also utilize an MPI layer. Other message passing interface layers can be used other than MPI such as Symmetric Hierarchical Memory Access (SHMEM) or Unified Parallel C (UPC)…” paragraph 0034) and the at least one of computation tasks and communication tasks are performed as part of an Allreduce collective operation ( AllReduce computation ) (“… FIG. 4B shows an example operation in an AllReduce computation. The MPI Collective can be implemented as a sequence of point-to-point MPI_Send and MPI_Recv calls (e.g., MPI Two Sided communications) to copy vectors to a participant. The receiver MPI Collective performs a selected operation (e.g., sum) to accumulate the final result vector. More specifically, in this example, two participants (e.g., a sender and a receiver) use MPI_Send and MPI_Recv to transfer a vector of data using an eager mechanism. As the individual eager packets arrive, the receiver NIC places content of the packets into an intermediate bounce buffer. The NIC software and/or hardware examines the packet, performs tag matching, and then copies the data into the buffer supplied by the MPI Collective as part of the MPI_Recv call. Once the MPI_Recv is complete, the receiver combines the data in the temporary buffer with its ongoing computation result (e.g., Compute Collective). The receiver and sender can repeat the sequence, with a different pairing of participants …” paragraph 0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Klenk with the teaching of Rimmer’721 because the teaching of Rimmer‘721 would improve the system of Memon and Klenk by providing a technique for providing a computed result to a requester. a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing . 07-22-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2020/0358721 A1 to Rimmer et al. (hereinafter referred to as Rimmer’721) and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al . as applied to claim 1 above, and further in view of U.S. Pub. No. 2022/0138021 A1 to Rimmer et al. (hereinafter referred to Rimmer’021) . As to claim 2, Memon as modified by Rimmer’721 and Klenk teaches the device of claim 1, however it is silent with reference to wherein the network interconnect comprises a Remote Direct Memory Access (RDMA)-capable Network Interface Controller (NIC) and wherein the first processing unit and second processing unit communicate with one another using RDMA capabilities of the RDMA-capable NIC. Rimmer’021 teaches wherein the network interconnect comprises a Remote Direct Memory Access (RDMA)-capable Network Interface Controller (NIC) and wherein the first processing unit and second processing unit communicate with one another using RDMA capabilities of the RDMA-capable NIC ( a remote direct memory access (RDMA)-enabled NIC ) (“… As is described herein, network interface device 450 can provide network access for transmitting packets to other platforms or receiving packets from other platforms in connection with parallel computation. Network interface device 450 can include various software, devices, and ports that prepare packets for transmission to a network or other medium or process packets received from a network or other medium. In some examples, a network interface device 450 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some examples, a network interface device 450 can refer to one or more of: a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, SmartNlC, router, switch, forwarding element, infrastructure processing unit (IPU), or data processing unit (DPU) …” paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Rimmer’721 and Klenk with the teaching of Rimmer’021 because the teaching of Rimmer’021 would improve the system of Memon, Rimmer’721 and Klenk by providing a direct memory access from the memory of one computer into that of another without involving either one's operating system . 07-22-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2020/0358721 A1 to Rimmer et al. (hereinafter referred to as Rimmer’721) and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al. and further in view of U.S. Pub. No. 2015/0235339 A1 to Soum et al . as applied to claim 7 above, and further in view of U.S. Pub. No. 2003/0020621 A1 to Kessler et al . As to claim 8, Memon as modified by Rimmer’721 and Klenk teaches the device of claim 7, however it is silent with reference to wherein the CPU and the DPU are to exchange a set of memory addresses and associated keys for sending and receiving control messages via the network interconnect. Soum teaches wherein the CPU and the DPU are to exchange a set of memory addresses ( memory address exchanges ) (“… The invention also provides a device for generating procedural textures for carrying out the above described method, wherein data exchanges between the CPU and the GPU consist in memory address exchanges in a unified CPU and GPU memory, said memory being subdivided into a plurality of areas: [0037] an area M0, which contains the list of filters to be activated; [0038] an area M1, which contains the best suited target CPU or GPU of each filter; [0039] an area M2, which contains the working buffers of the rendering engine; [0040] areas M3 and M4, which contain the programs associated with the filters, in their CPU versions and in their GPU versions …” paragraph 0036). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Rimmer’721 and Klenk with the teaching of Soum because the teaching of Soum would improve the system of Memon, Rimmer’721 and Klenk by a seamless technique for exchanging information between varying domains. Kessler teaches associated keys for sending and receiving control messages via the network interconnect ( Client Key Exchange Operation 423) (“… A network element acting as a router, switch, access to a storage farm, etc., may establish one or more secure sessions. Macro security operations enable the network element to establish multiple secure sessions without consuming large amounts of system resources. Moreover, the secure sessions can be established faster with macro security operations…For example, the coprocessor 212 may receive 3 requests to establish secure SSL 3.0 sessions. If the server full handshake operation 701 is implemented, then the host processor 201 can establish the secure sessions with 3 calls to the coprocessor 212. The execution units 216-217 can perform the 3 operations in parallel. A more granular set of macro security operations may be implemented on the server similar to the macro security operations described in FIG. 4 and FIG. 5. For example, the macro security operations described in FIG. 4 and FIG. 5 may be implemented on the server 403 that has received 2 requests for secure sessions. After the host processor 201 calls the coprocessor 212 to perform the client key exchange operation 423 for each of the two requested sessions, the server 403 receives a third request for a secure session. The host processor 201 calls the coprocessor 212 to perform the security negotiation operation 409 for this third secure session request. Although the request unit 214 of the coprocessor 212 issues the security negotiation operation 409 to one of the execution units 216-217 after issuing two client key exchange operations 423 to two of the execution units 216-217, the one of the execution units 216-217 that performs the security negotiation operation 409 will complete execution of the operation 409 before the other two of the execution units 216-217 complete execution of their operations (assuming the security negotiation operation 409 requires less time than the key exchange operation 423). Hence, operations from the host processor 201 may be issued to the execution units 216-217 in order, but completed by the execution units 216-217 out of order…” paragraphs 0049/0050). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Rimmer’721, Klenk and Soum with the teaching of Kessler because the teaching of Kessler would improve the system of Memon, Rimmer’721, Klenk and Soum by a seamless technique for establishing one or more secure sessions (Kessler paragraph 0049) . 07-22-aia AIA Claim s 9, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2020/0358721 A1 to Rimmer et al. (hereinafter referred to as Rimmer’721) and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al . as applied to claim 1 above, and further in view of U.S. Pub. No. 2011/0113083 A1 to Shahar . As to claim 9, Memon as modified by Rimmer’721 and Klenk teaches the device of claim 1, however it is silent with reference to wherein the control message is to identify at least one of a type of the reduction operation, a number of elements in the reduction, an address of an input vector for the reduction operation, and an address of an output vector. Shahar teaches wherein the control message is to identify at least one of a type of the reduction operation, a number of elements in the reduction, an address of an input vector for the reduction operation, and an address of an output vector ( when the computing task comprises a collective function such as MPI_REDUCE and MPI_ALLREDUCE ) (“…System 20 comprises an offload manager 48, typically a server that is connected to network 28. For each computing task scheduled by job scheduler 44, offload manager 48 configures at least some of switches 32, as well as some of nodes 24, to perform the computing task efficiently. In particular, when the computing task comprises a collective function such as MPI_REDUCE and MPI_ALLREDUCE, the offload manager configures switches 32 to carry out some of the processing associated with the collective function execution, thereby offloading the compute nodes. These offloading techniques are explained in greater detail below. Offload manager 48 comprises an interface 52 for connecting to network 28, and a processor 56 that carries out the configuration methods described herein …”paragraphs 0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Rimmer’721 and Klenk with the teaching of Shahar because the teaching of Shahar would improve the system of Memon, Rimmer’721 and Klenk by a seamless technique for configuring switches or nodes to allow for task offloading. As to claim 11, Shahar teaches the device of claim 1, wherein the second processing unit is to compute a result of at least a portion of the reduction operation ( MPI_REDUCE function ), maintain the result in an accumulate buffer ( a single node-level result/ single interim result) , and broadcast the result to the first processing unit ( each switch is notified of its parent switch in the tree, and of its lower-level tree elements (compute nodes or switches)) (“… For a given switch that lies on a path belonging to the collection tree, the offload manager configures the switch to forward interim results of the collective function (received from compute nodes in the group either directly or via one or more other switches) to a given switch that is "higher" along the collection tree. In other words, each switch is notified of its parent switch in the tree, and of its lower-level tree elements (compute nodes or switches)…The offload manager configures the selected root switch to reduce the interim result it receives to a single end result. If the collective function specifies that the end result is sent to a single target process (e.g., in an MPI_REDUCE function), the offload manager configures the root switch to forward the end result to the node running that process. If the collective function specifies that the end result is sent to all the nodes (e.g., in an MPI_ALLREDUCE function), the offload manager configures the root switch to forward the end result to all the nodes in the group (e.g., using multicast)…The method begins with the software processes, which run on the compute nodes in the group, producing interim results of the collective function, at a process execution step 70. Each compute node in the group reduces the interim results produced by its local processes to a single node-level result, at a node-level reduction step 74. The actual reduction operation depends on the type of collective function. For example, for a summation operation, the node-level result comprises a sum of the interim results produced by the processes of the node. For a collective function that finds the maximum value of the data, the node-level result comprises the maximal value of the interim results produced by the processes of the node. For a compute node that runs only a single process, the node-level result is equal to the interim result produced by the single process. For collective operations that do not involve reduction operations but rather data exchange between processes (e.g., MPI_ALLTOALL, MPI_GATHER and MPI_SCATTER), the switches along the collection tree reduce the number of exchanged messages, synchronize message flow and thus reduce fabric congestion…The network switches belonging to the collection tree reduce the interim results they receive, at a switch-level reduction step 82. In each switch 32, CPU 40 reduces the interim results received at the switch (directly from nodes 24 or from other switches) to a single interim result, also referred to as a switch-level result. The actual reduction operation depends on the type of collective function, as explained above with regards to the node-level reduction operation...end result calculation step 90… outhput step 94 …” paragraphs 0050/0051/0054/0056/0058/0059). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Rimmer’721 and Klenk with the teaching of Shahar because the teaching of Shahar would improve the system of Memon, Rimmer’721 and Klenk by a seamless technique of returning a result to a requester after task offloading. As to claim 12, Shahar teaches the device of claim 11, wherein the second processing unit is to broadcast the result to a processing unit of another device in addition to broadcasting the result to the first processing unit ( Sending the end result to multiple nodes can be performed, for example, by sending a multicast message ) (“… The root switch outputs the end result, at an output step 94. For example, if the collective function comprises an MPI_REDUCE function, the root switch sends the end result to the designated target node. If the collective function comprises an MPI_ALLREDUCE function, the root switch sends the end result to all the nodes in the group. Sending the end result to multiple nodes can be performed, for example, by sending a multicast message …” paragraph 0058). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Rimmer’721 and Klenk with the teaching of Shahar because the teaching of Shahar would improve the system of Memon, Rimmer’721 and Klenk by a seamless technique of returning a result to a requester after task offloading . 07-22-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2020/0358721 A1 to Rimmer et al. (hereinafter referred to as Rimmer’721) and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al . as applied to claim 1 above, and further in view of U.S. Pub. No. 2005/0223118 A1 to Tucker et al . As to claim 10, Memon as modified by Rimmer’721 and Klenk teaches the device of claim 1, however it is silent with reference to wherein the first processing unit is to periodically poll a predetermined memory location to check for a completion message from the second processing unit. Tucker teaches to wherein the first processing unit is to periodically poll a predetermined memory location to check for a completion message from the second processing unit ( polling a Completion Queue) (“… Sends, RDMA Reads, and RDMA Writes are posted to a Send Queue. Receives are posted to a Receive Queue (i.e., receive buffers with data that are the target for incoming Send messages). Another queue called a Completion Queue is used to signal a Verbs consumer when a Send Queue WQE completes, when such notification function is chosen. A Completion Queue may be associated with one or more work queues. Completion may be detected, for example, by polling a Completion Queue for new entries or via a Completion Queue event handler …” paragraph 0019). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Tucker because the teaching of Tucker would improve the system of Memon and Rimmer’721 by providing a technique for providing a data structure for storing and determining the completion of a process or execution and thus allowing for optimal processing . 07-21-aia AIA Claims 14-16, 18, 19, 21 and 22 are rejecte d under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2009/0043910 A1 to Barsness et al. and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al. As to cla im 14, Memon teaches a system, comprising: an endpoint ( Host CPU(s) 210) , wherein the endpoint is to perform application-level tasks for an operation in parallel with one or both of computation tasks and communication tasks (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory…” paragraph 0020), wherein the application-level tasks are to be performed on a first processing unit (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory…” paragraph 0020), and wherein the computation task is to be offloaded by the first processing unit to the second processing unit tasks (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory …” paragraph 0020). Memon is silent with reference to an endpoint that belongs to a collective, perform application-level tasks for a collective operation, wherein the first processing unit is to send a control message to a second processing unit to initialize the second processing unit and initiate a reduction operation by pre-allocating a buffer contained in memory of the second processing unit and a reduction operation. Barsness teaches an endpoint that belongs to a collective ( Compute Node 110) and perform application-level tasks for a collective operation ( Application program 420 executes collective operations by calling software routines in parallel communications library 422 ) (“… FIG. 4 sets forth a block diagram of an exemplary compute node as introduced above and shown in FIG. 1. The compute node 110 of FIG. 4 includes a plurality of computer processors 410, each with an arithmetic logic unit (ALU) 411 as well as random access memory (`RAM`) 412. Processors 410 are connected to RAM 412 through a high-speed memory bus 414. Also connected to the high-speed memory bus 414 is a bus adapter 416. The bus adapter 416 connects to an extension bus 418 that connects to other components of the compute node. Stored in RAM 412 is an application program 420, a module of computer program instructions that carries out parallel, user-level data processing using parallel algorithms. Also stored in RAM 412 is a parallel communication library 422, a library of computer program instructions that carry out parallel communications among compute nodes, including point to point operations as well as collective operations. Application program 420 executes collective operations by calling software routines in parallel communications library 422…Collective operations are implemented with data communications among the compute nodes of an operational group. Collective operations are those functions that involve all the compute nodes of an operational group. A collective operation is an operation, a message-passing computer program instruction that is executed simultaneously, that is, at approximately the same time, by all the compute nodes in an operational group of compute nodes. Such an operational group may include all the compute nodes in a parallel computer (100) or a subset all the compute nodes. Collective operations are often built around point to point operations. A collective operation requires that all processes on all compute nodes within an operational group call the same collective operation with matching arguments …” paragraphs 0044/0057). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon with the teaching of Barsness because the teaching of Barsness would improve the system of Memon by providing a collective communication operation that performs global reduction operation on values from all ranks of communicator and distributes the result back to all ranks. Klenk teaches wherein the first processing unit is to send a control message to a second processing unit to initialize the second processing unit ( In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 300) and initiate a reduction operation by pre-allocating a buffer contained in memory of the second processing unit ( For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302) (“… In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 300 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU 300. For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 300. The front end unit 315 receives pointers to one or more command streams. The front end unit 315 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 300 .…” paragraph 0066) and a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Barsness with the teaching of Klenk because the teaching of Klenk would improve the system of Memon and Barsness by providing a technique for providing computing resources for optimal processing. As to claim 15, Barsness teaches the system of claim 14, wherein the collective operation comprises an Allreduce collective ( all reduce operation) (“… One type of collective operation is an all reduce operation. An all reduce operation combines all the elements provided in an input buffer of each processor in the group using a common operation and then returns the combined value in an output buffer on all nodes. An all reduce OR operation is an all reduce operation where the operator on the data is a bitwise "OR" operation, where the "OR" is done on a bit-by-bit basis as is known in the art. In the all reduce OR operation herein, the search information on each node is combined to give a search result for the in-memory database …” paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Klenk with the teaching of Barsness because the teaching of Barsness would improve the system of Memon and Klenk by providing a collective communication operation that performs global reduction operation on values from all ranks of communicator and distributes the result back to all ranks. As to claim 16, Memon teaches the system of claim 15, wherein the first processing unit is network ( over the network) connected to the second processing unit ( “…The request for the coprocessor resource (in particular, here, memory) is transmitted from the client/application side, over the network, to the functional coprocessor/server side of FIG. 5 …” paragraph 0052), wherein the first processing unit is to utilize a first memory device of the endpoint ( host memory) , and wherein the second processing unit is to utilize a second memory device of the endpoint ( coprocessor device memory) (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory …” paragraph 0020). As to claim 18, Memon teaches the endpoint of claim 14, further comprising: a second endpoint that also belongs to the collective ( Host CPU(s) 210) , wherein the second endpoint also is to perform application-level tasks for the collective operation in parallel with one or both of computation tasks and communication tasks for the collective operation ( coprocessor device memory) (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory …” paragraph 0020). a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing. As to clam 19, Memon teaches an endpoint, comprising: a host ( Host CPU(s) 210 ) (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory…” paragraph 0020); and a Data Processing Unit (DPU) that is network-connected with the host, wherein the DPU ( Coprocessors ) comprises a DPU daemon that is to coordinate offload with the host through a network interconnect and service on behalf of the host (“…Coprocessors typically have a “master-slave” relationship relative to the normal host CPU(s) 210 that runs the applications—an application is typically run on the host CPU(s) while certain computational tasks are offloaded to coprocessors for increased performance. Compute APIs, that is, APIs 305 that are used by applications to leverage coprocessors, typically have explicit functions to offload computation and move data between host memory and coprocessor device memory…” paragraph 0020). Memon is silent with reference to wherein the DPU comprises a DPU daemon that is to coordinate a collective offload with the host through a network interconnect and service a collective operation on behalf of the host, wherein after receiving an initialization signal from the host, the DPU pre-allocates a buffer contained in memory in preparation for a collective operation and a reduction operation. Barsness teaches wherein the DPU comprises a DPU daemon that is to coordinate a collective offload with the host through a network interconnect ( global combining network ) and service a collective operation on behalf of the host (“… a query in a parallel computer system with multiple nodes. The efficiency of the parallel computer system is increased by offloading collective operations on node data to the global combining network. The global combining network performs collective operations such as minimum, maximum, sum, and logical functions such as OR and XOR… FIG. 7 shows a query 700 for illustrating an example of query optimization utilizing network extension hardware. The query 700 operates on the Employee 600 table described above with reference to FIG. 6. The query 700 selects the maximum salary from the Employees database table 600. To optimize this query, the query optimizer recognizes that the query has a maximum function (Select max (Salary)) for records in the database stored in the nodes. The query optimizer can then determine that the collective Max operation of the query can be processed on the global combining network as described further below. Offloading this processing to the ALUs on the global combining network rather than performing the function on a single node processor effectively utilizes the network extensions of the global combining network global network …” Abstract/0066). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon with the teaching of Barsness because the teaching of Barsness would improve the system of Memon by providing a collective communication operation that performs global reduction operation on values from all ranks of communicator and distributes the result back to all ranks. Klenk teaches wherein after receiving an initialization signal from the host, the DPU pre-allocates a buffer contained in memory in preparation for a collective operation ( For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302) (“… In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 300 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU 300. For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 300. The front end unit 315 receives pointers to one or more command streams. The front end unit 315 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 300 .…” paragraph 0066) and a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Barsness with the teaching of Klenk because the teaching of Klenk would improve the system of Memon and Barsness by providing a technique for providing computing resources for optimal processing. As to claim 21, Barsness teaches the endpoint of claim 19, wherein the DPU daemon is to broadcast results of the collective operation (“broadcast” collective operation ) to the host and to hosts of other endpoints belonging to a collective (“… Some collective operations have a single originating or receiving process running on a particular compute node in an operational group. For example, in a “broadcast” collective operation, the process on the compute node that distributes the data to all the other compute nodes is an originating process. In a `gather` operation, for example, the process on the compute node that received all the data from the other compute nodes is a receiving process. The compute node on which such an originating or receiving process runs is referred to as a logical root …” paragraph 0060). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Klenk with the teaching of Barsness because the teaching of Barsness would improve the system of Memon and Klenk by providing a collective communication operation that performs global reduction operation on values from all ranks of communicator and distributes the result back to all ranks. a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing. As to claim 22, Barsness teaches the endpoint of claim 19, wherein the collective operation comprises at least one of Allreduce, Iallreduce, Alltoall, Ialltoall, Alltoallv,Ialltoally, Allgather, Scatter, Reduce, and Broadcast ( all reduce operation) (“… One type of collective operation is an all reduce operation. An all reduce operation combines all the elements provided in an input buffer of each processor in the group using a common operation and then returns the combined value in an output buffer on all nodes. An all reduce OR operation is an all reduce operation where the operator on the data is a bitwise "OR" operation, where the "OR" is done on a bit-by-bit basis as is known in the art. In the all reduce OR operation herein, the search information on each node is combined to give a search result for the in-memory database …” paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Klenk with the teaching of Barsness because the teaching of Barsness would improve the system of Memon and Klenk by providing a collective communication operation that performs global reduction operation on values from all ranks of communicator and distributes the result back to all ranks. a reduction operation (“… A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device…Scalable in-network computations, such as a reduction operation, can be performed in the network 100 by off-loading the computation to the logic 130 in the network device 110 (or devices) rather than performing the computations on one of the endpoints or, as described in the conventional solutions using a ring-scheme algorithm, by spreading the computation around all of the participating endpoints…” Abstract/paragraphs 0047). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon and Rimmer’721 with the teaching of Rimmer’721 because the teaching of Rimmer’721 would improve the system of Memon and Rimmer’721 by providing a technique for providing computing resources for optimal processing . 07-22-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2009/0043910 A1 to Barsness et al. and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al . as applied to claim 16 above, and further in view of U.S. Pub. No. 2022/0138021 A1 to Rimmer et al. (hereinafter referred to Rimmer’021) . As to claim 17, Memon as modified by Barsness and Klenk teaches the system of claim 16, however it is silent with reference to wherein the first processing unit is to communicate with the second processing unit using a Remote Direct Memory Access (RDMA)-capable Network Interface Controller (NIC). Rimmer’021 wherein the first processing unit is to communicate with the second processing unit using a Remote Direct Memory Access (RDMA)-capable Network Interface Controller (NIC) ( a remote direct memory access (RDMA)-enabled NIC ) (“… As is described herein, network interface device 450 can provide network access for transmitting packets to other platforms or receiving packets from other platforms in connection with parallel computation. Network interface device 450 can include various software, devices, and ports that prepare packets for transmission to a network or other medium or process packets received from a network or other medium. In some examples, a network interface device 450 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some examples, a network interface device 450 can refer to one or more of: a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, SmartNlC, router, switch, forwarding element, infrastructure processing unit (IPU), or data processing unit (DPU) …” paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Barsness and Klenk with the teaching of Rimmer’021 because the teaching of Rimmer’021 would improve the system of Memon, Barsness and Klenk by providing a direct memory access from the memory of one computer into that of another without involving either one's operating system . 07-22-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0114254 A1 to Memon et al. in view of U.S. Pub. No. 2009/0043910 A1 to Barsness et al. and further in view of U.S. Pub. No. 2021/0036881 A1 to Klenk et al . as applied to claim 19 above, and further in view of U.S. Pub. No. 2007/0294680 A1 to Papakipos et al . As to claim 20, Memon as modified by Barsness and Klenk teaches the endpoint of claim 19, however it is silent with reference to wherein the DPU daemon is to assume full control over the collective operation after receiving an initialization signal from the host. Papakipos teaches wherein the DPU daemon is to assume full control ( execute compute kernels) over the collective operation after receiving an initialization signal from the host ( initialize one or more processing elements including processors, coprocessors, processor/coprocessor cores, functional units) (“…At run-time, an application 20 invokes the runtime system 10 by calling into one of its Language-Specific Interfaces (LSI) 100 to perform operations predefined in the application 20. In some embodiments, the LSI 100 includes multiple modules, each module providing an Application Program Interface (API) to the runtime system 10 for applications written in a specific programming language. The runtime system 10 is configured to spawn zero or more threads, initialize one or more processing elements including processors, coprocessors, processor/coprocessor cores, functional units, etc., as necessary, and execute compute kernels associated with the predefined operations on the processing elements accessible to the runtime system 10. In some embodiments, a compute kernel is an executable program or subroutine that runs on one or more processing elements that are part of a parallel processing computer system to perform all or parts of one or more operation requests. In some embodiments, the runtime system 10 includes dynamically linked libraries, static libraries, or a combination of both types of libraries. In some embodiments, the runtime system 10 includes one or more standalone programs that run independently of user applications, with which the other components of the runtime system 10 (e.g., its libraries) communicate…” paragraph 0036). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Memon, Barsness and Klenk with the teaching of Papakipos because the teaching of Papakipos would improve the system of Memon, Barsness and Klenk by providing an executable program or subroutine that runs on one or more processing elements that are part of a parallel processing computer system to perform all or parts of one or more operation request ( Papakipos paragraph 0036) . Response to Arguments 07-37 AIA Applicant's arguments filed 02/18/26 have been fully considered but they are not persuasive. Applicants argues in substance that (1) the 103 rejection of the Creamer prior art in view of Rimmer and Klenk prior arts is improper because the Creamer prior art does not correlate or correspond to the patent number (10,261,912) provided, (2) the motivation for combining the Memon, Rimmer and Klenk prior arts is improper or confusing, and (3) the applied references do not teach or suggest a first processing unit is to offload a computation task comprising a reduction operation. As to point (1), in response to Applicant’s argument, the Examiner is withdrawing the rejection of claim 1 as rejected by Creamer in view of Rimmer and Klenk prior arts. As to point (2), examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine , 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones , 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc. , 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the Klenk prior art is applied to provide buffers for sending messages between first processing unit and second processing unit. The buffer as the described computing resource allows for optimal processing by seamlessly allowing the first processing unit to communicate messages with the second processing unit. Additionally, the Appeals Board will determine the appropriateness of the motivation statement. As to point (3), the Klenk prior art discloses a pull mechanism technique for coordinating a computation among a plurality of processors in communication over a network, where at least a portion of the computation (tasks) is off-loaded from the processors to one or more network devices. The off-loading of computation (tasks) includes “reduction operation” as discloses in the abstract and paragraph 0047). Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES E ANYA whose telephone number is (571)272-3757. The examiner can normally be reached Mon-Fir. 9-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached on 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHARLES E ANYA/Primary Examiner, Art Unit 2194 Application/Control Number: 17/949,817 Page 2 Art Unit: 2194 Application/Control Number: 17/949,817 Page 3 Art Unit: 2194 Application/Control Number: 17/949,817 Page 4 Art Unit: 2194
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