Attorney’s Docket Number: T101304US02
Filing Date: 09/21/2022
Claimed Priority Date: 09/23/2021 (PRO 63/247,797)
Applicants: Nguyen et al.
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the Amendments filed on 10/09/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s elections without traverse of Group I Invention, directed to a method of making a semiconductor device, corresponding to claims 1-14, in the reply filed on 05/19/2025, is acknowledged.
With regards to the species restriction between Species 1-4, examiner agrees with the applicants reasoning, leaving the species restriction withdrawn.
Accordingly, pending in this application are claims 1-14, with claims 15-20 stand withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group Invention, there being no allowable generic or linking claim.
Response to Amendment
The Amendment filed on 10/09/2025, responding to the Office action mailed on 06/09/2025, has been entered. The present Office action is made with all the suggested amendments and arguments being fully considered.
The replacement drawing sheet filed on 10/09/2025 is acknowledged and renders the specification objection from the office action moot. Accordingly, this objection is withdrawn.
Applicant amendments to the Specification have overcome the objections to the Specification, accordingly, this objection is hereby withdrawn
Applicant’s amendments to claims 2, 4, and 6 overcome the claim objections and rejections under 35 U.S.C. 112, as previously formulated in the same Office action.
Applicant has declined to amend independent claim 1 in response to the rejections under 35 U.S.C. 103 previously formulated in the Non-Final Office action mailed on 12/14/2023. However, the previously presented prior art remains relevant, and new grounds for rejection are presented below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Faralli et al (US 20150001651 A1, Hereinafter Faralli) in view of Kaija (US 20190359480 A1).
Regarding claim 1, Faralli (e.g., Fig 1-12 [0020]-[0058] Device 300 along with the steps to form device 100/200 [0045]) shows A method, comprising:
forming a micro-electromechanical system (MEMS) component (device 300 diaphragm 319, Fig 5 [0045]) on a device side surface of a first semiconductor substrate (350a of wafer 350 Fig 6), the first semiconductor substrate having a backside surface opposite the device side surface (350b, Fig 6)), and forming at least one wire connection electrically coupled to and spaced from the MEMS component (wire 237 connects the MEMs component containing die 10 to a substrate [0062]);
forming a first polymer seal structure (401, Fig 8 on surface 400a [0049]) corresponding to the location of the MEMS component and extending from a device side surface of a second semiconductor substrate, the second semiconductor substrate having a backside surface opposite the device side surface of the second semiconductor substrate (400b on wafer 400);
bonding the second semiconductor substrate to the first semiconductor substrate using the first polymer seal structure (Fig 10 shows wafer 400 and 350 are joined using 401 joined to 351, to become bonding regions 222), the device side surface of the second semiconductor substrate facing the MEMS component on the device side surface of the first semiconductor substrate and forming a top surface of a cavity (Space 25, Fig 1), the first polymer seal structure forming sidewalls of the cavity, the cavity including the MEMS component (e.g., Fig 5 shows 319 in the cavity 25), and the wire connection (37, Fig 4) being outside of the cavity;
performing backside processing on the first semiconductor substrate to form a trench through the first semiconductor substrate, the trench at least partially surrounding the MEMS component; ([0053] trench 14 and air gap 21 formed by backside processing “etched from the back”, in combination with previously formed trench 14, now form a trench extending through substrate 300) to form a trench through the first semiconductor substrate (e.g., air gap 21), the trench (e.g., combined trench 21,14)
patterning a second polymer seal structure (Adhesive layer 236/36, made of a bioadhesive film, for example a DAF, Figs 14 and 1) extending from a device side (600a) surface of a third semiconductor substrate ( wafer 600, Fig 14 referred as 220 in fig 4) corresponding to the MEMS component locations on the first semiconductor substrate; and
bonding the third semiconductor substrate (Fig 15, 600) to the backside surface of the first semiconductor substrate using the second polymer seal structure to form a gap beneath the MEMS component, the second polymer seal structure forming sidewalls of the gap, the device side surface of the third semiconductor substrate forming a bottom surface of the gap (Fig 15 shows wafer-wafer bonding using adhesive regions 236 on side 600a, where there is a gap formed beneath the MEMs component) .
While Faralli shows wire connections spaced apart from cavity containing the MEMs component, it is silent about having a bond pad used in the wire connection.
Kaija (e.g., Fig 3 [0041]-[0043]), in a related field of MEMs device packaging, Teaches forming bond pads (113) coupled with bonding wires (101) to connect a MEMs die to a digital die.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the a bond pad coupled to a wire in the method of Faralli, because bond pads are known in the semiconductor packaging art as means to provide electrical connectivity between a chip and a substrate through a bonding wire, as suggested by Kaija, and implementing a known electrical connection arrangement for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 9, Faralli shows forming a MEMS component further comprises forming a transducer, a temperature sensor, a pressure sensor, an optical sensor, a micromirror, an acoustic sensor, or a bulk acoustic wave (BAW) device ([0006] shows A MEMS sensor generally comprises a micromechanical detection structure, which transduces a mechanical quantity to be detected (for example, a set of acoustic waves, a pressure, etc.) into an electrical quantity).
Regarding Claim 10, Faralli shows forming a MEMS component further comprises forming a BAW device ([0006] shows A MEMS sensor generally comprises a micromechanical detection structure, which transduces a mechanical quantity to be detected (for example, a set of acoustic waves, a pressure, etc.) into an electrical quantity).
Claims 2, 3, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Faralli in view of Kaija further in view of Takano et al (US 20200127633 A1, Hereinafter Takano)
Regarding claim 2, Faralli in view of Kaija shows a MEMs packaging device that mentions the process of dicing a wafer to result in a plurality of MEMs devices (Faralli, Claim 16) and the MEMS devices positioned in the cavities (space 25) and having air in the trenches and in the gaps (air gap 21 [0024][0053]). However, it does not disclose using a photoresist to pattern saw streets in a surface.
Takano (e.g., Fig 2A-2D [0006]-[0013][0060]-[0065]), on the other hand and in a related field of MEMS device packaging, teaches the dicing process of BAW components with air cavities it also teaches:
performing backside processing on the backside surface of the second semiconductor substrate and patterning a photoresist to define saw streets between a plurality of MEMS components formed on the first semiconductor substrate (Fig 2B/2C shows depositing a mask 32 to form a trench through a street 34) ;
etching through the backside surface of the second semiconductor substrate in the saw streets to expose the device side surface of the first semiconductor substrate in the saw streets (plasma etch is used to create trenches [0061])
dicing the first semiconductor substrate and the third semiconductor substrate by cutting through the first semiconductor substate and the third semiconductor substrate in the saw streets to form individual MEMS devices, (BAW devices are diced along the exposed streets, creating separate components (FIG 2D)
Takano teaches this plasma etching method in dicing BAW devices to pattern a suitable width of streets and using photolithography can result in rounded corners to reduce the risk of the BAW component cracking and/or chipping to thereby increase reliability of the BAW component ([0063]).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the method of using resist/etch to define saw streets in a singulation process for MEMS devices in the structure of Faralli in view of Kaija as taught by Takano, to reduce stress on the MEMs device during singulation and increase the reliability of the device.
Regarding claim 3, Faralli (e.g., Fig 1-3, 4, 5 Fig 6-12 [0020]-[0056]) in view of Kaija shows
mounting an individual MEMS device to a die mount area on a package substrate (Fig 15,16 second die 235 and 240) having a conductive lead using a die attach material (Fig 5 shows MEMS component die 310 attached to a second die 35 using die attach material 42, electrically coupled by wire 37 [0042]);
electrically coupling the bond pad of the MEMS device to the conductive lead using a bond wire or a ribbon bond (wire 37 );
covering the individual MEMS device, the bond pad, the bond wire or ribbon bond, and a portion of the package substrate with a mold compound ([0043] packaging material 245 or 45 coats the MEMS device, the wire connection 237 or 37 and the package substrate 235); and
leaving a portion of the package substrate (35, 40) having electrical terminals exposed from the mold compound to form a microelectronics device package (underside of 35 facing away from the MEMS die 310 is not covered by the mold compound forming a processing circuit ([0042]).
With regard to the limitation relating to bond pads, see comments in paragraph 14-16 regarding claim 1, as they would be considered repeated here.
Regarding claim 4, Faralli (Fig 4/5, [0035]) shows the package substrate (240, support 40) is a multilayer substrate.
Allowable Subject Matter
Claims 5-8, 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 10/09/2025 have been fully considered but they are not persuasive.
In response to applicant's arguments that the (primary) reference (Faralli) fails to show particular limitations and/or features of applicant’s invention, it is noted that the examiner is entitled to the broadest reasonable interpretation of the claim language, and that the limitations argued are not recited in the body of the rejected claims, as detailed below. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues:
“Applicant submits that Faralli fails to teach at least this limitation ( Claim 1- forming a micro-electromechanical system (MEMS) component on a device side surface of a first semiconductor substrate). In forming the rejection, the Examiner equates the MEMS component to diaphragm 219 of Faralli. The diaphragm 219 is not formed on any surface of the die 10 Instead, the diaphragm 219 is formed within the die, not on any surface of the die 10.”
The examiner responds:
The examiner respectfully disagrees.
As seen in the abstract, Faralli mentions “A diaphragm is formed in or on the die and faces the first surface.” Further, Par [0045] and Fig 5 show the diaphragm (319) on the surface in another embodiment. New ground of rejections include this embodiment.
The applicant argues:
“The trenches 14 are formed through frontside etching of the semiconductor wafer instead of backside processing ("With reference to FIG. 7, the first wafer 350 is etched from the front by a silicon etching step so as to laterally define the trenches 14 and the springs 15" [0048] of Faralli, emphasis added)”.
Examiner responds:
The examiner respectfully disagrees.
While partial trenches are defined using a front etch step, Claim 1 requires “performing backside processing on the first semiconductor substrate to form a trench through the first semiconductor substrate.” While the front etch step defines an initial trench, it does not form the trench through the entire semiconductor substrate.
As such, regarding the limitation "performing backside processing on the first semiconductor substrate to form a trench through the first semiconductor substrate", the examiner maintains that Faralli (e.g. , Fig. 11 and Par [0053]) does shows a step of performing backside processing on the first semiconductor substrate (e.g., wafer 350 is thinned from the second face 350b) to form a trench through the first semiconductor substrate (e.g., air gap 21 formed by backside processing, in combination with previously formed trench 14, now form a trench extending through substrate 300), the trench (e.g., combined trench 21,14) at least partially surrounding the MEMS.
The examiner does not understand the step "performing backside processing on the first semiconductor substrate to form a trench through the first semiconductor substrate" expressly requiring the entirety of the trench to be formed by the step of backside process as argued. Therefore, the art of Faralli is still applicable and the rejection stands.
Applicant is encouraged to capture aspects of the invention in the body of the claim so as to unambiguously distinguish his invention from the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose MEMs devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814