DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/22/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022.
Claim 1: Shultz discloses a capacitor structure (Fig. 8 stacked capacitor #8 ) comprising: a substrate ( [0029] Fig. 1 is a structure that may be constructed upon a substrate surface [0042] Fig. 8 is a side view of such an exemplary stacked, 2-sided capacitor 8 similar to the stacked linear capacitor structure of Fig. 1)); an insulating layer (Fig. 8 #830) disposed on the substrate; a capacitor (Fig. 8 #8) comprising: a first electrode layer (Fig. 8 first signal side connection #820 ) disposed on the insulating layer (Fig. 8 dielectric material #830); a second electrode layer (Fig. 8 second signal side connection #822) disposed on the first electrode layer (Fig. 8 #820); and a dielectric layer (Fig. 8 #830) disposed between the first electrode layer (Fig. 8 #820) and the second electrode layer (Fig. 8 #830); a Shielding layer (Fig.8 #800) disposed in the insulating layer ( Fig. 8 between layers of #830) and located between the first electrode layer (Fig. 8 #820) and the substrate (as discussed above); a first connection terminal ([0042] an opening in the ground shield layers #800 permits conductive coupling to the first signal side connection #820) electrically connected to the first electrode layer (Fig. 8 #820); and a second connection terminal ([0042] and to the second signal side connection #822 ) electrically connected to the second electrode layer (Fig. 8 #822).
Shultz does not appear to disclose the first electrode layer is located between the second electrode layer and the shielding layer in a direction perpendicular to a top surface of the substrate.
However, Ding(#716) teaches the first electrode layer (Fig. 6: Ca) is located between the second electrode layer (Fig. 6: Cb) and the shielding layer (Fig. 6: SH) in a direction perpendicular to a top surface of the substrate ( Fig. 6 shows Ca is between Cb and SH in a direction perpendicular to a top surface of the substrate #101) and the shielding layer is a metal layer ( [0083] The light-shielding layer SH, the third capacitor electrode Cc and the first power signal bus VDD may use metal materials or allow materials, such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), or the like ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ding (#716) with Shultz to implement the first electrode layer is located between the second electrode layer and the shielding layer in a direction perpendicular to a top surface of the substrate because placing the first electrode layer between the second layer and the shielding layer protects it from electromagnetic interference.
Claim 2: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above). Regarding claim 2, Shultz discloses the shielding layer (Fig. 8 #800) is further disposed between the second electrode layer (Fig. 8 #830) and the substrate ([0029] Fig. 1 is a structure that may be constructed upon a substrate surface [0042] Fig. 8 is a side view of such an exemplary stacked, 2-sided capacitor 8 similar to the stacked linear capacitor structure of Fig. 1).
Claim 4 is rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022 as applied to claims 1-2 above, and further in view of Shoji et al.; US 9,329,281; 02/2013.
Claim 4: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose the resistance of the shielding layer is less than resistance of the substrate.
However, Shoji teaches the resistance of the shielding layer ( Col 24. Line 63 the light shielding layer ) is less than resistance ( Col 24. Line 67 - Col 25. Line 7 from the viewpoint of antistatic properties of the deposition substrates, the surface resistivity measured with respect to the surface of the reflective layer opposite to the surface in contact with the support is preferably not more than 1.0 x 1012 Ω/□ (□ in Ω/□ the unit means square and has no dimension)) of the substrate ( Col 25. Line 1 the deposition substrates).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shoji with Shultz and Ding(#716) to implement the resistance of the shielding layer less than resistance of the substrate because this allows the shielding layer to prevent unwanted currents from flowing through the substrate.
Claims 5 and 7 are rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022 as applied to claims 1-2 above, and further in view of Yuan et al.; US 20220102461; 02/2020.
Claim 5: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose a vertical projection of part of the second electrode layer is located on the first electrode layer.
However, Yuan teaches a vertical projection ( [0006] an orthographic projection of the first transparent electrode plate on the substrate is located within an orthographic projection of the second transparent electrode place on the substrate ) of part of the second electrode layer ( Fig. 1. #312 ) is located on the first electrode layer ( Fig. 1 #311 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yuan with Shultz and Ding(#716) to implement a vertical projection of part of the second electrode layer located on the first electrode layer because this will improve charge transport and overall electrode performance.
Claim 7: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose a vertical projection of the entire first electrode layer is located on the shielding layer.
However, Yuan teaches a vertical projection of the entire first electrode layer ( Fig. 1 #311) is located on the shielding layer ( [0091] The light-shielding layer SHL is electrically connected to the first electrode 323b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yuan with Shultz and Ding(#716) to implement a vertical projection of the entire first electrode layer located on the shielding layer because it will help minimize parasitic capacitance and improve the capacitor’s performance.
Claims 8- 10, 12 and 18 are rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022 as applied to claims 1-2 above, and further in view of Zhang et al.; US 2024/0049525 A1; 03/2021
Claim 8: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose a vertical projection of the entire second electrode layer is located on the shielding layer.
However, Zhang teaches a vertical projection (see Fig.3) of the entire second electrode layer (Fig. 3 #162) is located on the shielding layer (Fig. 3 #131).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Shultz and Ding(#716) to implement a vertical projection of the entire second electrode layer located on the shielding layer because this will maximize capacitance density and improve performance especially in high-frequency applications.
Claim 9: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose the second electrode layer comprises: an overlapping portion overlapped with the first electrode layer; and a non-overlapping portion not overlapped with the first electrode layer.
However, Zhang teaches the second electrode layer (Fig. 3 #162) comprises: an overlapping portion ( see Fig. 3 left side #162 overlaps with #161) overlapped with the first electrode layer (Fig. 3 #161) ; and a non-overlapping portion ( see Fig. 3 #162 extends from the overlapping portion with #161 from the left edge of the figure to the right past the middle of the figure) not overlapped with the first electrode layer (Fig. 3 #161).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Shultz and Ding(#716) to implement the second electrode layer that comprises: an overlapping portion overlapped with the first electrode layer; and a non-overlapping portion not overlapped with the first electrode layer because this approach will maximize the capacitance while maintaining the desired voltage rating.
Claim 10: Shultz, Ding(#716), and Zhang disclose the capacitor structure of claim 9 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose an upper surface of the non-overlapping portion is lower than a top surface of the overlapping portion.
However, Zhang teaches an upper surface of the non-overlapping portion is lower (see Fig. 3 where #162 drops down after the overlapping portion) than a top surface of the overlapping portion ( see Fig. 3 #162 is higher in the overlapping portion than the long section that is lower).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Shultz and Ding(#716) to implement an upper surface of the non-overlapping portion is lower than a top surface of the overlapping portion because this is due to the way the capacitor is constructed since the non-overlapping area does not contribute to the capacitance of the capacitor.
Claim 12: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose the dielectric layer is further disposed between the second electrode layer and the insulating layer.
However, Zhang teaches the dielectric layer (Fig. 3 first conductive layer SD) is further disposed between the second electrode layer (Fig. 3 second electrode #162) and the insulating layer (Fig. 3 first insulating layer #132).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Shultz and Ding(#716) to implement the dielectric layer further disposed between the second electrode layer and the insulating layer because this increases capacitance and provides mechanical support, allowing for smaller plate separations and higher capacitance values.
Claim 18: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose a passivation layer disposed on the dielectric layer and the second electrode layer, wherein the first connection terminal is electrically connected to the first electrode layer through the passivation layer and the dielectric layer, and the second connection terminal is electrically connected to the second electrode layer through the passivation layer.
However, Zhang teaches a passivation layer (Fig. 3 passivation layer #135) disposed on the dielectric layer (Fig. 3 #136) and the second electrode layer ( Fig. 3 a second electrode #162), wherein the first connection terminal ( Fig. 3 first connection electrode FD11 ) is electrically connected to the first electrode layer (Fig. 3 AN) through the passivation layer (Fig. 3 #135) and the dielectric layer (Fig. 3 #136), and the second connection terminal ( Fig. 3 second connection electrode FD12 ) is electrically connected to the second electrode layer ( Fig. 3 #162 ) through the passivation layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Shultz and Ding(#716) to implement a passivation layer disposed on the dielectric layer and the second electrode layer, wherein the first connection terminal is electrically connected to the first electrode layer through the passivation layer and the dielectric layer, and the second connection terminal is electrically connected to the second electrode layer through the passivation layer because the passivation layer primarily protects the material from environmental factors and it also provides mechanical and electrical stability.
Claims 13 - 16 are rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022 as applied to claims 1-2 above, and further in view of Fernandes et al.; US 11,587,864 B2; 12/2021
Claim 13: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose the first connection terminal is an outermost layer of the capacitor structure.
However, Fernandes teaches the first connection terminal ( Col. 3 lines 33-35 One terminal is terminal #701 and may be taken from metal layer #134) is an outermost layer of the capacitor structure (Col. 3 lines 36-38 In one implementation, terminals #701 and #703 are exposed to input/output (I/O) pads from the integrated circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fernandes with Shultz and Ding(#716) to implement the first connection terminal is an outermost layer of the capacitor structure because of ease of connection.
Claim 14: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose a top surface of the first connection terminal is not covered by other components in the capacitor structure.
However, Fernandes teaches a top surface of the first connection terminal (Col 3. line 33 terminal #701) is not covered by other components in the capacitor structure (Col. 3 lines 36-38 In one implementation, terminals #701 and #703 are exposed to input/output (I/O) pads from the integrated circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fernandes with Shultz and Ding(#716) to implement a top surface of the first connection terminal is not covered by other components in the capacitor structure because it facilitates electrical connections with the terminal.
Claim 15: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose the second connection terminal is an outermost layer of the capacitor structure
However, Fernandes teaches the second connection terminal (Col. 3 lines 35–36 The other terminal is terminal #703 which may be provided by metal layer portion #119) is an outermost layer of the capacitor structure (Col. 3 lines 36-38 In one implementation, terminals #701 and #703 are exposed to input/output (I/O) pads from the integrated circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fernandes with Shultz and Ding(#716) to implement the second connection terminal is an outermost layer of the capacitor structure because of ease of connection
Claim 16: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose a top surface of the second connection terminal is not covered by other components in the capacitor structure.
However, Fernandes teaches a top surface of the second connection terminal (Col 3. line 35 terminal #703) is not covered by other components in the capacitor structure (Col. 3 lines 36-38 In one implementation, terminals #701 and #703 are exposed to input/output (I/O) pads from the integrated circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fernandes with Shultz and Ding(#716) to implement a top surface of the second connection terminal is not covered by other components in the capacitor structure because it facilitates electrical connections with the terminal.
Claim 17 is rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022 as applied to claims 1-2 above, and further in view of Cheng et al.; US 12,317,762; 08/2022
Claim 17: Shultz and Ding(#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding(#716) appear to disclose spacers disposed on sidewalls of the first electrode layer.
However, Cheng teaches spacers ( Col. 10 lines 9-10 first and second sidewall spacers #613 and #623) disposed on sidewalls (Col. 10 line 9 side wall spacers) of the first electrode layer (Fig. 8 top electrode #801).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cheng with Shultz and Ding(#716) to implement spacers disposed on sidewalls of the first electrode layer because spacers are primarily used to prevent short circuits and maintain electrical isolation between two electrodes.
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Shultz; US 2006/0061935 A1; 09/2004 in view of Ding(#716) et al.; US 2024/0381716 A1; 05/2022 as applied to claims 1-2 above, and further in view of Ding(#624) et al.; US 11094624 B2; 04/2019.
Claim 19: Shultz and Ding (#716) disclose the capacitor structure of claim 1 (as discussed above).
Neither Shultz nor Ding (#716) appear to disclose the first connection terminal and the second connection terminal comprise under-bump metallization, a bump, or a combination thereof.
However, Ding (#624) teaches the first connection terminal (Col 2 line 61 first interconnection structure #57A) and the second connection terminal (Col 2 lines 62-63 second interconnection structure #57B) comprise under-bump metallization, a bump, or a combination thereof (Col. 3 lines 6-8 Each of the plurality of connection structures #73 may include an under bump metallization (UBM) #69 and a bump #71 disposed on the UBM #69).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ding (#624) with Shultz and Ding(#716) to implement the first connection terminal and the second connection terminal comprise under-bump metallization, a bump, or a combination thereof because most components are attached to larger systems using surface mount technology and under-bump metallization (UBM) creates a wider area for soldering or bonding.
Response to Amendments/Arguments
Applicant’s arguments, see pages 6 - 8 of the remarks, filed 08/22/2025, with respect to the rejection of claim 1 and the corresponding dependent claims under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Ding (#716).
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817