DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10 December 2025 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al (US Publication 20230068882).
Regarding claim 1, Hsu teaches a semiconductor device, comprising:
a substrate (Fig. 3, 303);
an electrostatic discharge (ESD) device including a diode and configured to control an electrostatic discharge in the semiconductor device (Fig. 3, 204);
a plurality of metal rails embedded within the substrate (Fig. 3, BM0-BM5, para 26, 42, and 44); and
a power grid embedded within the substrate (Fig. 3, BM0-BM5, BV0-BV4, BAP, BRV, BVC), at least one of the plurality of metal rails being part of the power grid and being directly connected to the Electrostatic Discharge (ESD) device (Fig. 3, 204, PG/PD, para 52),
wherein the plurality of metal rails are buried in the substrate below a top of the substrate (Fig. 3, BM0-BM5 below top of 303), and
wherein the ESD device is disposed on the power grid in a direction perpendicular to a top surface of the substrate (Fig. 3, 204 on BM0 perpendicular to top of 303, the ESD device is three dimensional, therefore, at least one side of the ESD device will be vertical and thus perpendicular to and disposed on a horizonal top surface of the substrate).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication 20230068882) in view of Correale, JR et al (US Publication 20190213298).
Regarding claim 2, Hsu teaches the limitations of claim 1 upon which claim 2 depends.
Hsu does not specifically teach wherein at least one of the plurality of metal rails is a heat sink in the semiconductor device.
Correale teaches wherein at least one of the plurality of metal rails is a heat sink in the semiconductor device (para 34, "efficient heat distribution, decoupling capacitance, and noise mitigation").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to further include the plurality of metal rails is a heat sink in the semiconductor device as taught by Correale to improve thermal management and thus reliability and operability of the device.
Claims 3-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication 20230068882) in view of Hiblot et al (US Publication 20230178478).
Regarding claims 3-5, Hsu teaches the limitations of claim 1 upon which claim 3 depends.
Hsu does not specifically teach:
[claim 3] further comprising at least one trench embedded in the substrate, the at least one of the plurality of metal rails being embedded in the at least one trench
[claim 4] wherein a thickness of the at least one trench is larger than a width of the at least one trench
[claim 5] wherein a depth of the at least one trench is controlled to modify a capacitance value in the semiconductor device
Hiblot teaches:
[claim 3] further comprising at least one trench embedded in the substrate, the at least one of the plurality of metal rails being embedded in the at least one trench (Fig. 8, 15).
[claim 4] wherein a thickness of the at least one trench is larger than a width of the at least one trench (Fig. 8, 15).
[claim 5] wherein a depth of the at least one trench is controlled to modify a capacitance value in the semiconductor device (Fig. 8, 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to include embedded power rails including trenches thicker than they are wide to control capacitance as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Regarding claims 6 and 7, Hsu teaches the limitations of claim 1 upon which claims 6 and 7 depend.
Hsu does not specifically teach:
[claim 6] further comprising at least one decoupling capacitance part integrated with at least two of the plurality of metal rails in the one power grid to provide a high signal integrity and high density routing
[claim 7] further comprising at least one decoupling capacitance part between adjacent ones of the plurality of metal rails, the at least one decoupling capacitance part being embedded inside the substrate
Hiblot teaches:
[claim 6] further comprising at least one decoupling capacitance part integrated with at least two of the plurality of metal rails in the one power grid to provide a high signal integrity and high density routing (Fig. 9, 20, dielectric liner in trench 15).
[claim 7] further comprising at least one decoupling capacitance part between adjacent ones of the plurality of metal rails, the at least one decoupling capacitance part being embedded inside the substrate (Fig. 9, 20, dielectric liner in trench 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to further include embedded power rails including trenches with a thin film dielectric liner as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Regarding claim 8, Hsu teaches the limitations of claim 1 upon which claim 8 depends.
Hsu teaches further comprising at least two through-silicon vias (TSVs) connected with the power grid at two sides of the semiconductor device (Fig. 3, 318, 320, 322, para 48 and 51); and
a standard cell on at least one of the power lines (Fig. 3, 112, para 28 and 45).
Hsu does not specifically teach at least one decoupling capacitance part in the power grid, the at least one decoupling capacitance part being embedded in the substrate between power lines.
Hiblot discloses at least one decoupling capacitance part in the power grid, the at least one decoupling capacitance part being embedded in the substrate between power lines (Fig. 9, 20, dielectric liner in trench 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to further include embedded power rails including trenches with a thin film dielectric liner as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Regarding claims 10-12, Hsu teaches the limitations of claim 1 upon which claim 10 depends.
Hsu teaches:
[claim 10] a standard cell on the power line (Fig. 3, 112, para 28 and 45).
[claim 12] wherein the standard cell includes at least one of a diode, a P-channel metal-oxide semiconductor (PMOS), a N-channel metal-oxide semiconductor (NMOS), a transistor, and a resistor (Fig. 3, 112, para 28 and 45).
Hsu does not specifically teach:
[claim 10] further comprising: at least one decoupling capacitance part between a power line and a ground line in the power grid;
[claim 11] wherein the at least one decoupling capacitance part includes a high-k dielectric part, the high-k dielectric part being between the power line and the ground line and defining a capacitor.
Hiblot teaches
[claim 10] at least one decoupling capacitance part between a power line and a ground line in the power grid (Fig. 9, 20, dielectric liner in trench 15); and
[claim 11] wherein the at least one decoupling capacitance part includes a high-k dielectric part, the high-k dielectric part being between the power line and the ground line and defining a capacitor. (Fig. 9, 20, dielectric liner in trench 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to further include at least one decoupling capacitance part between the power line and ground line in the power grid as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Regarding claims 13 and 14, Hsu teaches the limitations of claim 1 upon which claims 13 and 14 depend.
Hsu teaches
[claims 13 and 14] a first metal rail and a second metal rail (Fig. 3, BM0-BM5);
[claim 13] and at least one via between the first metal rail and the second metal rail in the power grid (Fig. 3, 320)
Hsu does not specifically disclose how the metal rails are disposed / embedded in substrate and therefore does not specifically disclose:
[claims 13 and 14] wherein the plurality of metal rails includes:
a first metal rail, the first metal rail being part of the power grid and embedded in a deep trench inside the substrate,
a second metal rail, the second metal rail being part of the power grid and embedded in a shallow trench above the first metal rail;
[claim 14] a high-k dielectric part between the first metal rail and the second metal rail in the power grid.
Hiblot discloses
[claims 13 and 14] a first metal rail, the first metal rail being part of the power grid and embedded in a deep trench inside the substrate (Fig. 8, 15);
a second metal rail, the second metal rail being part of the power grid and embedded in a shallow trench above the first metal rail (Fig. 8, 15); and
[claim 14] a high-k dielectric part between the first metal rail and the second metal rail in the power grid (Fig. 9, 20, dielectric liner in trench 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to include a first and second metal rail as part of a power grid embedded in in a deep and shallow trench respectively and a high-k dielectric part between them as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Regarding claim 15, Hsu teaches a semiconductor device, comprising:
a substrate (Fig. 3, 303);
at least one Power Distribution Network (PDN) layer embedded within the substrate (Fig. 3, BAP), the at least one PDN layer being a single layer and including a power line (Fig. 3, 336), a ground line (Fig. 3, 340),
a standard cell embedded within the substrate, the standard cell disposed on a portion of the at least one PDN layer in a direction perpendicular to a top surface of the substrate (Fig. 3, 112, para 28 and 45, the standard cell is three dimensional, therefore, at least one side of the standard cell will be vertical and thus perpendicular to a horizonal top surface of the substrate),
the portions of the at least one PDN layer are embedded within the substrate to be surrounded by material of the substrate (Fig. 3, 336, 340, BAP embedded and surrounded by 303, para 42).
Hsu does not specifically disclose a high-k dielectric part between the power line and the ground line
Hiblot discloses a high-k dielectric part between the power line and the ground line (Fig. 9, 20, dielectric liner in trench 15)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to include a high-k dielectric part between the power line and the ground line and a back-end-of-line layer as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Hsu as modified teaches wherein the power line, the ground line (Hsu, Fig. 3, 336, 340), the high-k dielectric part (Hiblot, Fig. 9, 20, dielectric liner in trench 15), and the portions of the at least one PDN layer are embedded within the substrate to be surrounded by material of the substrate (Fig. 3, 336, 340, 112 embedded in substrate).
Regarding claim 16, Hsu as modified teaches the limitations of claim 15 upon which claim 16 depends.
Hsu teaches further comprising back-end-of-line layers on the substrate (Fig. 3, 306, para 42).
Regarding claim 17, Hsu teaches a semiconductor device, comprising:
a substrate (Fig. 3, 303);
at least one top Power Distribution Network (PDN) layer embedded within the substrate (Fig. 3, BAP), the at least one top PDN layer including a first power line (Fig. 3, 336), a first ground line (Fig. 3, 340),
at least one bottom PDN layer embedded within the substrate (Fig. 3, BM5), the at least one bottom PDN layer including a second power line (Fig. 3, 350), a second ground line (Fig. 3, 356),
at least one standard cell embedded within the substrate, the at least on standard cell disposed on a portion of the at least one top PDN layer in a direction perpendicular to a top surface of the substrate (Fig. 3, 112, para 28 and 45, the standard cell is three dimensional, therefore, at least one side of the standard cell will be vertical and thus perpendicular to a horizonal top surface of the substrate),
wherein the first and second power lines, the first and second ground lines, and the portions of the at least one top PDN layer are embedded within the substrate to be surrounded by material of the substrate (Fig. 3, 336, 340, 350, 356, BAP, and BM5 embedded in substrate 303).
Hsu does not specifically teach:
a first/second high-k dielectric part between the first/second power line and the first/second ground line.
Hiblot discloses
a first/second high-k dielectric part between the first/second power line and the first/second ground line (Fig. 9, 20, dielectric liner in trench 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hsu to include a first/second high-k dielectric part between the first/second power line and the first/second ground line and back-end-of-line layers on the substrate as taught by Hiblot to address ESD as well as reduce noise and voltage fluctuations in the device.
Regarding claim 18, Hsu as modified teaches the limitations of claim 17 upon which claim 18 depends.
Hsu teaches further comprising back-end-of-line layers on the substrate (Fig. 3, 306, para 42).
Regarding claim 19, Hsu as modified teaches the limitations of claim 15 upon which claim 19 depends.
Hsu teaches wherein the standard cell includes at least one of a diode, a P-channel metal-oxide semiconductor (PMOS) transistor, an N-channel metal-oxide semiconductor (NMOS) transistor, and a resistor (Fig. 3, 112, para 28 and 45).
Regarding claim 20, Hsu as modified teaches the limitations of claim 17 upon which claim 20 depends.
Hsu teaches wherein the standard cell includes at least one of a diode, a P-channel metal-oxide semiconductor (PMOS) transistor, an N-channel metal-oxide semiconductor (NMOS) transistor, and a resistor (Fig. 3, 112, para 28 and 45).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 15, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The rejection above uses newly cited references to Hsu, Correale, and Hiblot.
Conclusion
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818