DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (US Publication No. 2022/0020859).
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Regarding claim 1, Cho discloses a semiconductor device, comprising: an isolation region Fig 15B, ST or Fig 16, ST; at least one transistor Fig 15B, PR1 or Fig 16, TR2 comprising a gate region Fig 15B, GE or Fig 16, GE, wherein the gate region is disposed on the isolation region Fig 15B, ST or Fig 16, ST; a via ¶0089 Fig 15B or Fig 16, LP disposed through a portion of the isolation region and on a signal line Fig 15B, SI or Fig 16, SI; and a gate contact Fig 15B, GC or Fig 16, UP disposed on the gate region Fig 15B or Fig 16, wherein the via ¶0089 Fig 15B or Fig 16, LP is connected to the gate contact Fig 15B, GC or Fig 16, UP and the signal line Fig 15B, SI or Fig 16, SI is connected to the gate region through the via ¶0089 Fig 15B or Fig 16, LP and the gate contact Fig 15B, GC or Fig 16, UP.
Regarding claim 2, Cho discloses wherein the signal line Fig 15B, SI or Fig 16, SI is disposed in a same metallization level as a power element Fig 15B, POR1/POR2.
Regarding claim 3, Cho discloses wherein the power element comprises a power rail ¶0041-0042.
Regarding claim 4, Cho discloses wherein the at least one transistor further comprises a source/drain region Fig 15A, SD1, and the semiconductor device further comprises an additional via disposed through another portion of the isolation region and on the power element Fig 15A.
Regarding claim 5, Cho discloses further comprising a source/drain contact disposed on the source/drain region, wherein the additional via Fig 15A, EP is connected to the source/drain contact Fig 15A.
Regarding claim 6, Cho discloses wherein the via contacts a side surface of the gate region Fig 14A.
Regarding claim 8, Cho discloses wherein the via is disposed adjacent the gate region Fig 15B and Fig 16.
Regarding claim 9, Cho discloses further comprising at least one additional transistor comprising an additional gate region, wherein the additional gate region is disposed on the isolation region, and wherein the via is disposed between the gate region and the additional gate region Fig 15B and Fig 16.
Regarding claim 10, Cho discloses wherein the gate contact is further disposed on the additional gate region, and wherein the signal line is connected to the additional gate region through the via and the gate contact Fig 15B and Fig 16.
Regarding claim 11, Cho discloses a semiconductor device, comprising: an isolation region Fig 15B, ST or Fig 16, ST; at least one transistor Fig 15B, PR1 or Fig 16, PR1 comprising a gate region Fig 15B, GE or Fig 16, GE and source/drain region Fig 15A, SD1; a first via ¶0089 Fig 15B or Fig 16, LP disposed through a first portion of the isolation region Fig 15B, ST or Fig 16, ST and on a signal line Fig 15B, SI or Fig 16, SI, wherein the first via ¶0089 Fig 15B or Fig 16, LP connects the signal line Fig 15B, SI or Fig 16, SI to the gate region Fig 15B, GE or Fig 16, GE; and a second via Fig 15A, EP disposed through a second portion of the isolation region and on a power element Fig 15A, POR1/POR2, wherein the second via connects the power element to the source/drain region Fig 15A.
Regarding claim 12, Cho discloses wherein the signal line is disposed in a same metallization level as the power element Fig 15A-15B and Fig 16.
Regarding claim 13, Cho discloses wherein the power element comprises a power rail¶0041-0042.
Regarding claim 14, Cho discloses a gate contact Fig 15B, GC or Fig 16, UP on the gate region, wherein the first via Fig 15B, LP or Fig 16, LP is connected to the gate contact Fig 15B, GC or Fig 16, UP on and the signal line Fig 15B, SI or Fig 16, SI on is connected to the gate region through the first via and the gate contact Fig 15A-15B and Fig 16.
Regarding claim 15, Cho discloses wherein the first via contacts a side surface of the gate region Fig 14A.
Regarding claim 16, Cho discloses a source/drain contact on the source/drain region, wherein the second via Fig 15A, EP is connected to the source/drain contact and the power element Fig 15A, POR1/POR2 is connected to the source/drain region through the second via and the source/drain contact Fig 15A.
Regarding claim 17, Cho discloses an integrated circuit, comprising: at least one transistor Fig 15B, PR1 comprising a gate region Fig 15B, GE and source/drain region Fig 15A, SD1; a first via ¶0089 Fig 15B or Fig 16, LP on a signal line Fig 15B, SI, wherein the first via connects the signal line Fig 15B, SI to the gate region Fig 15B, GE; and a second via Fig 15A, EP on a power element Fig 15A, POR1/POR2, wherein the second via connects the power element Fig 15A, POR1/POR2 to the source/drain region Fig 15A, SD1; wherein the signal line Fig 15A, SI and Fig 15B, SI is disposed in a same metallization level as the power element Fig 15A-15B.
Regarding claim 18, Cho discloses a gate contact Fig 15B, GC on the gate region Fig 15B, GE1, wherein the first via ¶0089 Fig 15B or Fig 16, LP is connected to the gate contact Fig 15B, GC and the signal line Fig 15B, SI is connected to the gate region through the first via and the gate contact Fig 15A-15B.
Regarding claim 19, Cho discloses wherein the first via contacts a side surface of the gate region Fig 14A.
Regarding claim 20, Cho discloses a source/drain contact on the source/drain region, wherein the second via Fig 15A, EP is connected to the source/drain contact and the power element Fig 15A, POR1/POR2 is connected to the source/drain region through the second via and the source/drain contact Fig 15A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US Publication No. 2022/0020859) in view of Chen et al (US Publication No. 2023/0036522).
Regarding claim 7, Cho discloses all the limitations but is silent on the clock signal line.
Whereas Chen discloses wherein the signal line comprises a clock signal line ¶0097-0099.
Cho and Chen are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Cho because they are from the same field of endeavor.
Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cho and incorporate the teachings of Chen to improve device synchronization and timing.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811