DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 June 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is unclear as to what constitutes “substantially planar” as substantially is an adverb that means to a large degree, by considerable amount, or essentially in the main points. It is not clear at what degree the side surface would be considered substantially planar vs nonplanar – essentially what are the specific boundaries of this limitation? The specification provides no guidance. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. It is recommended that the word ‘substantially’ be deleted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-15, 17-22, 24, and 26-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leung et al (US Publication 20160035651).
Regarding claim 1¸Leung teaches a method, comprising:
providing a leadframe strip (Fig. 2, lead frame structure 20, para 33), wherein the leadframe strip comprises multiple leadframes (Fig. 2, lead frames 22 and 28, para 33),wherein each leadframe of the multiple leadframes comprises a diepad (Fig. 2, die attach regions 27, para 33) and a first row of leads arranged at a first side of the diepad (Fig. 2, terminals 21, 23, 25, para 33), wherein at least one lead of the first row of leads is physically separated from the diepad by a gap (Fig. 2, terminal 25 physically separated from die attach region 27);
arranging semiconductor components on the leadframes (Fig. 3 and 4, device dies 40, para 36);
encapsulating the leadframes and the semiconductor components with an encapsulation material (Fig. 3, para 38);
forming first gaps in the encapsulation material, wherein the first gaps extend through the encapsulation material in a direction perpendicular to a main surface of the leadframe strip (Fig. 3 and 5a, path X-X singulation cuts perpendicular to a main surface of lead frame structure 20), wherein after forming the first gaps leads of the first rows of leads are at least partly exposed from the encapsulation material (Fig. 5a, terminals 21, 23, and 25 exposed from encapsulation material, para 39, "The purpose of these cuts is to remove the encapsulation in the vicinity of the I/ O terminals 21, 23, 25 so that they can be electroplated");
after forming the first gaps extending fully through the encapsulation material (para 39, "The cuts may extend through the encapsulation and the lead frame material but terminate at a tape material (not illustrated) such that each lead frame in a row remains mechanically connected to the tape"), forming a metal coating on the exposed leads based on an electroplating process (Fig. 3, para 40, "Following the first series of cuts, electroplating (process step 38) of the I/ O terminals 21, 23, 25 is carried out so as to form the metal side pads 54"); and
after forming the metal coating on the exposed leads, forming second gaps in the encapsulation material, wherein the second gaps intersect with the first gaps and extend fully through the encapsulation material in the direction perpendicular to the main surface of the leadframe strip (Fig. 5a-c, para 41, "Following the electroplating step, a second series of parallel cuts are made in lead frame structure 20 (process step 39)"),
wherein the metal coating is formed on the exposed leads after forming the first gaps and before forming the second gaps (Fig. 3, first singulation cut then electroplating then final singulation steps 36-39, para 40-41),
wherein: the leadframe strip comprises a peripheral frame and at least one support rail (Fig. 2, lead frame 20 peripheral frame portion surrounding die attach regions 27, support rail portion of lead frame 20 between respective leads 21, 23, and 25), and
at least some of the leads of the leadframes are connected to at least one of the peripheral frame or the at least one support rail (Fig. 2, leads 21, 23 and 25 respective portions connected to support rail),
wherein tie bars are used as an electric connection to the at least some of the leads during the electroplating process (Fig. 5c, tie bars 29, para 39, "tie bars 29 may be included to provide mechanical support for the I/ O terminals 25, 23 on the lead frame structure 20. The tie bars 29 also provide electrical connection to the lead frame structure 20. The tie bars 29 are arranged to be severed, following electroplating, during a second series of parallel cuts"), and
wherein the leadframe strip is encapsulated by the encapsulation material (para 38, "the array of lead frames 22, 28 are encapsulated in a mould compound. The encapsulation defines a first set of opposing side walls for the leadless packaged semiconductor device.") and the tie bars are completely intact during the electroplating process (para 39, "The tie bars 29 are arranged to be severed, following electroplating").
Regarding claim 2, Leung teaches the limitations of claim 1 upon which claim 2 depends.
Leung teaches wherein each leadframe of the multiple leadframes further comprises a second row of leads arranged at a second side of the diepad opposite to the first side of the diepad (Fig. 2 and 5a, leads 21, 23, and 25 on opposite sides top and bottom of die attach regions 27).
Regarding claim 3, Leung teaches the limitations of claim 2 upon which claim 3 depends.
Leung teaches wherein at least one lead of the second row of leads is directly physically connected to the diepad (Fig. 2, terminal 21 physically attached to dis attach region 27).
Regarding claim 4, Leung teaches the limitations of claim 2 upon which claim 4 depends.
Leung teaches wherein, before forming the first gaps, the first row of leads of a first leadframe of the multiple leadframes is physically connected to the second row of leads of a second leadframe of the multiple leadframes neighboring the first leadframe (Fig. 2 and 4, all terminals of lead frame 20 physically connected).
Regarding claim 5, Leung teaches the limitations of claim 4 upon which claim 5 depends.
Leung teaches wherein, before forming the first gaps, there is no encapsulation material arranged between the first row of leads of the first leadframe and the second row of leads of the second leadframe (Fig. 2 and 3, molding performed after die bonding and wire bonding).
Regarding claim 6, Leung teaches the limitations of claim 4 upon which claim 6 depends.
Leung teaches wherein, during forming the first gaps, the first row of leads of the first leadframe is physically separated from the second row of leads of the second leadframe (Fig. 5a, para 39).
Regarding claim 7, Leung teaches the limitations of claim 2 upon which claim 7 depends.
Leung teaches wherein each of the semiconductor components comprises a drain contact, a gate contact and a source contact (Fig. 6b, drain contact below device and gate/source contacts on top of device), wherein the method further comprises:
electrically coupling at least one of the gate contact or the source contact of a respective semiconductor component with the first row of leads of the respective leadframe on which the respective semiconductor component is arranged (Fig. 4 and 6b, wire bonds between leads 25/23 and source/gate contacts of device, para 37), and
electrically coupling the drain contact of the respective semiconductor component to the second row of leads of the respective leadframe (Fig. 4 and 6b, bottom of 40 coupled to lead 21, para 37).
Regarding claim 8, Leung teaches the limitations of claim 1 upon which claim 8 depends.
Leung teaches wherein multiple singulated semiconductor packages are obtained by forming the second gaps (Fig. 3, final singulation 39, para 41).
Regarding claim 10, Leung teaches the limitations of claim 1 upon which claim 10 depends.
Leung teaches wherein the at least some of the leads of the leadframes are still connected to at least one of the peripheral frame or the at least one support rail after forming the first gaps (Fig. 5a, first gaps formed along X-X, leads of lead frames 22-28 still connected to portion of lead frame 20 after first cuts along X-X).
Regarding claim 11, Leung teaches the limitations of claim 1 upon which claim 11 depends.
Leung teaches wherein tie bars are used as an electric connection to the at least some of the leads during the electroplating process (para 16 and 39).
Regarding claim 12, Leung teaches the limitations of claim 1 upon which claim 12 depends.
Leung teaches wherein the first gaps are formed between the leadframes and extend in a first direction, wherein a dimension of the first gaps in the first direction is smaller than a dimension of the encapsulation material in the first direction (Fig. 5a - 6a, gaps between lead frames from first cuts smaller than thickness of encapsulation).
Regarding claim 13, Leung teaches the limitations of claim 12 upon which claim 13 depends.
Leung teaches wherein the first direction is substantially perpendicular to the at least one support rail (Fig. 5a - 6a, gap between lead frames along X-X perpendicular to support rail portion of lead frame 20).
Regarding claim 14, Leung teaches the limitations of claim 1 upon which claim 14 depends.
Leung teaches wherein all leads of the leadframes are exposed by forming the first gaps (para 39, leads 21, 23, and 25 exposed by first cuts).
Regarding claim 15, Leung teaches the limitations of claim 12 upon which claim 15 depends.
Leung teaches wherein the second gaps are formed between the leadframes and extend in a second direction substantially perpendicular to the first direction (Fig. 5c, Z-Z perpendicular to X-X).
Regarding claim 17, Leung teaches a semiconductor package, comprising:
a leadframe comprising a diepad and a first row of leads, wherein at least one lead of the first row of leads is physically separated from the diepad by a gap (Fig. 2, lead frame 20, diepad 27, leads 23/25 physically separated from diepad 27 by gap);
a semiconductor component arranged on the leadframe (Fig. 4, 40); and
an encapsulation material encapsulating the leadframe and the semiconductor component (Fig. 6a, para 38, "mould compound"), wherein the encapsulation material comprises a bottom surface arranged at a bottom surface of the semiconductor package, a top surface and a substantially planar side surface extending from the bottom surface to the top surface (Fig. 6a top, bottom, and substantially planar side surface of moulding),
wherein a side surface of at least one lead of the first row of leads is flush with the substantially planar side surface of the encapsulation material (Fig. 6a, leads 21-25 flush with the substantially planar side surface of the moulding), and
wherein the flush side surface of the at least one lead is covered by an electroplated metal coating (Fig. 6a, 54, para 39),
wherein the encapsulation material comprises two side surfaces that are devoid of exposed leads (Fig. 6a, 2 sides of device devoid of exposed leads),
wherein: the leadframe further comprises a portion of a tie bar, and
a side surface of the portion of the tie bar is flush with and surrounded by a side surface of the encapsulation material (Fig. 6a, tie bar flush with and surrounded by moulding side surface, see arrows pointing to flush tie bar surrounded by the moulding in annotated figure 6a below:).
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Regarding claim 18, Leung teaches the limitations of claim 17 upon which claim 18 depends.
Leung teaches wherein the bottom surface of the semiconductor package is planar (Fig. 6a-b, bottom surface of package is planar).
Regarding claim 19, Leung teaches the limitations of claim 17 upon which claim 19 depends.
Leung teaches wherein the bottom surface of the encapsulation material, a bottom surface of the diepad and a bottom surface of the at least one lead are arranged in a common plane (Fig. 6a, bottom surface of moulding, diepad, and leads arranged on a common plane).
Regarding claim 20, Leung teaches the limitations of claim 17 upon which claim 20 depends.
Leung teaches wherein the bottom surface of the semiconductor package is free of grooves between a bottom surface of the diepad and a bottom surface of the first row of leads (Fig. 6a, no grooves between diepad and leads 21-25).
Regarding claim 21, Leung teaches the limitations of claim 17 upon which claim 21 depends.
Leung teaches wherein the entire side surface of the at least one lead is flush with the side surface of the encapsulation material (Fig. 6a, side surfaces of 25 and moulding flush).
Regarding claim 22, Leung teaches the limitations of claim 17 upon which claim 22 depends.
Leung teaches wherein the entire side surface of the at least one lead is covered by the electroplated metal coating (Fig. 6a, 54, para 39).
Regarding claim 24, Leung teaches the limitations of claim 17 upon which claim 24 depends.
Leung teaches wherein the metal coating is devoid of gold (para 40, tin).
Regarding claim 26, Leung teaches the limitations of claim 17 upon which claim 26 depends.
Leung teaches wherein the side surface of the tie bar is uncovered by a metal coating (Fig. 6a, para 40, electroplating not performed on tie bars).
Regarding claim 27, Leung teaches the limitations of claim 17 upon which claim 27 depends.
Leung teaches wherein the semiconductor package is a flat no-leads package (Fig. 6a-b, para 2, QFN/DFN).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Leung et al (US Publication 20160035651) in view of Celaya et al (US Publication 20160190095).
Regarding claim 23, Leung teaches the limitations of claim 17 upon which claim 23 depends.
Leung does not specifically teach wherein a thickness of the metal coating is greater than 4 micrometers.
Celaya teaches wherein a thickness of the metal coating is greater than 4 micrometers (para 111, "a thickness ranging from about 0.5 microinches (12.7 nanometers) to about 3,000 microinches (76.2 micrometers)").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Leung to include the metal coating thickness as taught by Celaya in order to improve electrical conductivity and durability of the device.
Response to Arguments
Applicant’s arguments, filed 26 June 2026, with respect to claims 1 and 17 have been fully considered and are persuasive. In light of these arguments and the amendments made to claims 1 and 17 a new ground of rejection is described above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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