DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-8 of Request for Reconsideration – After Non-Final, filed 11/04/2025, with respect to the rejection(s) of claims 1-15 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of a newly found prior art reference, which teaches the limitations of “and a buffer layer, the buffer layer being formed between the plurality of source layers” as described below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2017/0162591 A1, hereinafter Choi ‘591) in view of Lee (US 2021/0242219 A1, hereinafter Lee ‘219), in view of the following arguments.
With respect to Claim 1 Choi ‘591 discloses a memory device (Figs 1-6) comprising:
a source line (PS, Fig 3B, Para [0052]) including a plurality of source layers (123/153/131, Fig 3B, Para [0084]);
a stack structure (141/143, Fig 3C, Para [0055]) formed on the source line (PS);
a cell plug (combined structure of CH/CAP/CO/ML, Fig 3D, Para [0060], hereinafter PLUG) contacting the source line (PS) by passing through the stack structure (141/143);
a slit (SA and SB, Fig 3E, Para [0061]) separating the stack structure (141/143) (arrangement disclosed in Fig 3E); and
Choi ‘591 fails to explicitly disclose and a buffer layer, the buffer layer being formed between the plurality of source layers; a source contact formed in the slit and contacting the source line.
Nevertheless, in a related endeavor (Fig 1A-4 of Lee ‘219), Lee ‘219 teaches and a buffer layer (ES1 and ES2, Fig 2K of Lee ‘219, Para [0114]), the buffer layer (ES1 and ES2) being formed between source layers (SL, Fig 2K of Lee ‘219); a source contact (CSL, Fig 2K of Lee ‘219, Para [0050]) formed in the slit (SLS, Fig 1B of Lee ‘219, Para [0050]) and contacting the source line (SL)(Fig 2K of Lee ‘219 discloses CSL in slit SLS and contacting source line SL).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘219’s teaching of and a buffer layer, the buffer layer being formed between the plurality of source layers; a source contact formed in the slit and contacting the source line into Choi ‘591’s memory device. The ordinary artisan would have been motivated to modify Choi ‘591 to add a buffer layer around the source layer, at least, because, as Lee ‘219 teaches in Para [0097] the etch stop layers protect the substrate and stack from being etched during etch steps in the manufacturing process. The ordinary artisan would be motivated to form the source contact in the slit and contacting the source line, at least because in general, using the slit structures to form a source contact is a well-known design for memory stacks and more specifically because the arrangement of having the contact (CSL of Lee ‘219) contact the second source line from the top of the structure, instead of the bottom, will simplify the manufacturing process for the device of Choi ‘591 as all processes can then be conducted from one side of the structure.
As incorporated, the buffer layer (ESL1 and ESL2 of Lee ‘219) would be on the top of source layer (123 of Choi ‘591) and the bottom of source layer (131 of Choi ‘591) so that the buffer layer (ESL1 and ESL2 of Lee ‘219) would be between the plurality of source layers 123, 153 and 131 of Choi ‘591.
Further, as incorporated the source contact (CSL of Lee ‘219) would be formed in the slit of Choi ‘591 and contact source line (113) of Choi ‘591.
With respect to Claim 2 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Choi ‘591 as modified by Lee ‘219 further discloses wherein the plurality of source layers (123/153/131) are formed of a conductive material (Para [0052] of Choi ‘591 disclose 123 and 131 include silicon and Para [0083] discloses 153 is grown from silicon layer 131), and wherein the buffer layer (ESL1 and ESL2 of Lee ‘219 as incorporated above) is formed of an insulating material (Para [0026 of Lee ‘219] discloses ESL1 and ESL2 as SiCN).
With respect to Claim 3 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Choi ‘591 further discloses wherein the plurality of source layers (123/153/131) are formed of at least one material that is selected from polysilicon, tungsten, and nickel, or a combination of selected materials (Para [0090] discloses 131 formed of polysilicon, Para [0083] discloses 153 is grown from 131 (polysilicon) and Para [0052] discloses 123 as formed of the same material as 131).
With respect to Claim 4 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Lee ‘219 further discloses wherein the buffer layer (ES1 and ES2 of Lee ‘219 as incorporated in Choi ‘591) is formed of at least one an oxide layer, a nitride layer, SiON, and SiCN (Para [0026 of Lee ‘219] discloses ESL1 and ESL2 as SiCN).
With respect to Claim 5 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Choi ‘591 further discloses wherein the cell plug (PLUG) is formed in a plug hole (H, Fig 3D of Choi ‘591, Para [0059]) that passes through the stack structure (141/143) and a landing hole (bottom of H) that passes through a portion of the source line (PS)(Fig 3D of Choi ‘591 discloses plug hole H extending partially through PS).
With respect to Claim 6 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 5, and Choi ‘591 further discloses wherein the cell plug (PLUG) comprises:
a core pillar (CO, Fig 3D of Choi ‘591, Para [0060]) formed in the plug hole (H) and the landing hole (bottom of H);
a channel layer (CH, Fig 3D of Choi ‘591, Para [0060]) surrounding the core pillar (CO); and
memory layers (ML, Fig 3D of Choi ‘591, Para [0060]) surrounding the channel layer (CH).
With respect to Claim 7 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 6, and Choi ‘591 further discloses wherein portions (DS and TI, Fig 3L of Choi ‘591, Para [0078]) of each of the memory layers (ML) are removed in an area (area of layer 127 as shown in Fig 3L of Choi ‘591, Para [0078]) in which the source line (PS) and the cell plug overlap (PLUG)(Fig 3L of Choi ‘591 discloses portions of ML removed in 127 and the source line and cell plug overlapping there).
With respect to Claim 8 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 6, and Choi ‘591 further discloses wherein the core pillar (CO) and the channel layer (CH) extend from an uppermost end (top of PLUG) to a lowermost end (bottom of PLUG) of the cell plug (PLUG) (Para [0060] of Choi ‘591 discloses CO extending through hole H and Fig 3L of Choi ‘591 discloses CH extending to bottom of PLUG).
With respect to Claim 9 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Choi ‘591 further discloses wherein the source line (PS) is formed of polysilicon including an impurity (Para [0090] discloses 131 formed of carbon doped polysilicon, Para [0083] discloses 153 is grown from 131 (carbon doped polysilicon) and Para [0052] discloses 123 as formed of the same material as 131).
With respect to Claim 10 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Choi ‘591 further discloses wherein the stack structure (141/143) includes conductive layers (143, Fig 3C of Choi ‘591, Para [0055]) and interlayer insulating layers (141, Fig 3C of Choi ‘591, Para [0055]) that are alternately stacked (alternatively stacked layers disclosed in Fig 3C of Choi’591).
With respect to Claim 14 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, and Choi ‘591 as modified by Lee ‘219 further discloses wherein the number of the buffer layers (ESL1 and ESL2 of Lee ‘219 as incorporated in Choi ‘591) is changed according to the number of the plurality of source layers (123/153/131)(As described above, ESL1 and ESL2 of Lee ‘219 are incorporated so that they are between source layers 123/153/131).
Choi ‘591 as modified by Lee ‘219 fails to expressly disclose wherein the number of the buffer layers is changed according to the number of the plurality of source layers.
However, Lee ‘219 teaches in Para [0097] the etch stop layers protect surrounding layers during the etching processes to form layers of the source line, therefore it would be obvious to a person having ordinary skill in the art to add additional buffer layers between seed layers as further source layers were needed to protect the existing layers from damage as the step of adding new source layers is repeated. Further, MPEP§2144.04 (VI)(B) and In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) cites duplication of parts as an obvious modification.
With respect to Claim 15 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 14, and Choi ‘591 as modified by Lee ‘219 further discloses wherein, when the number of the plurality of source layers (123/153/131) is N (N=3), the number of the buffer layers (ESL1 and ESL2 of Lee ‘219 as incorporated in Choi ‘591 as described above) is N-1 (2), and wherein N is a natural number greater than or equal to 2 (Choi ‘591 as modified by Lee ‘219 teaches an embodiment of N=2).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Choi ‘591 in view of Lee ‘219 and in further view of Zhang (US 2021/0375913 A1, hereinafter Zhang ‘913), in view of the following arguments.
With respect to Claim 11 Choi ‘591 as modified by Lee ‘219 discloses all limitations of the memory device of claim 1, but Choi ‘591 as modified by Lee ‘219 fails to explicitly disclose further comprising: a compensation plug formed below the cell plug in the source line.
Nevertheless, in a related endeavor (Fig 1 of Zhang ‘913), Zhang ‘913 teaches a compensation plug (122, Fig 1 of Zhang ‘913, Para [0047]) formed below (when viewing Fig. 1 of Zhang ‘913 upside-down) the cell plug (124, Fig 1 of Zhang ‘913, Para [0041]) in the source line (120, Fig 1 of Zhang ‘913, Para [0052]: 120, is in contact with source contact 132; hence 120 is a source line).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zhang ‘913’s a compensation plug formed below the cell plug in the source line into Choi ‘591 as modified by Lee ‘219’s device. The ordinary artisan would have been motivated to modify Choi ‘591 as modified by Lee ‘219 in the manner set forth above, at least, because, as Zhang ‘913 teaches in Para [0049], the plugs (122) enable body biasing for erase operations for 3D memory devices which would improve the operation of Choi ‘591 as modified by Lee ‘219’s device.
As incorporated, the compensation plug (122) of Zhang ‘913 would be used under the cell plug (PLUG) in the source line (PS) of Choi ‘591 as modified by Lee ‘219.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi ‘591 in view of Lee ‘219, in view of Zhang ‘913 and in further view of King (US 2004/0110332 A1, hereinafter King ‘332), in view of the following arguments.
With respect to Claim 12 Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913 discloses all limitations of the memory device of claim 11, and Zhang ‘913 discloses in Para [0047] that the doping level of the compensation plug (122) can be different than the doping level of the different than the source line (120), but Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913 fails to explicitly disclose wherein the compensation plug is formed of a material having an impurity concentration that is higher than that of the source line.
Nevertheless, in a related endeavor (Fig 14 of King ‘332), King ‘332 discloses teaches a memory device (Para [0029]: charge trapping device) that uses a different impurity (Para [0185] of King ‘332: arsenic) that provides a higher doping concentration (Para [0185] of King ‘332) than another material (Para [0185] of King ‘332: phosphorus) to a target area (1037, Fig. 14 of King ‘332, Para [0184]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of King ‘332 into the memory device Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913 to provide a compensation plug is formed of a material having an impurity concentration that is higher than that of the source line in the device of Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913. The ordinary artisan would have been motivated to modify Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913 in the manner set forth above for at least the purpose of improving charge trapping (King ’332, Para [0185]) and improve device switching speeds (King ‘332, Para [0292]).
As incorporated, the teachings of King ‘332 of a region having an impurity concentration that is higher than that of a second region so that the compensation plug (122) of Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913 has an impurity concentration that is higher than that of the source line (PS) of Choi ‘591 as modified by Lee ‘219 and further modified by Zhang ‘913.
With respect to Claim 13 Choi ‘591 as modified by Lee ‘219 as modified by Zhang ‘913 and further modified by King ‘332 discloses all limitations of the memory device of claim 12, and Zhang ‘913 further discloses wherein the impurity is a phosphorous or boron ion (Para [0043] of Zhang ‘913 discloses phosphorus as impurity for doping 120 and 122).
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898