DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (U.S. Publication No. 2021/0384072 A1; hereinafter Jin) in view of Xie et al. (U.S. Publication No. 2020/0343186 A1; hereinafter Xie)
With respect to claim 1, Jin discloses an integrated circuit structure, comprising: a plurality of conductive lines [110] along a same direction, one of the conductive lines having a break therein (see Figure 14); and an inter-layer dielectric (ILD) structure [101] having portions between adjacent ones of the plurality of conductive lines and having a dielectric plug portion [120] in a location of the break in the one of the conductive lines, the dielectric plug portion of the ILD structure continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines (see Figure 14 and ¶[0025] and ¶[0036]; no space is between [120] and [101] and both structures are formed of the same materials, therefore considered continuous), Jin fails to disclose the dielectric plug portion of the ILD structure having an inwardly tapering profile from top to bottom, however does disclose a slightly tapered bottom (see Figure 15). In the same field of endeavor, Xie teaches the dielectric plug portion [702] of the ILD structure having an inwardly tapering profile from top to bottom (see Figure 9). The inward tapering profile of Xie’s dielectric plug portion within Jin’s already bottom tapered dielectric plug portion allows for a more precise minimum feature size and minimum pitch while providing the proper electrical isolation between the conductive regions (see Xie ¶[0032]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
Claim(s) 2-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Xie as applied to claim 1 above, and further in view of Lee et al. (U.S. Publication No. 2019/0081233 A1; hereinafter Lee)
With respect to claim 2, the combination of Jin and Xie fails to explicitly disclose wherein the plurality of conductive lines comprises a conductive barrier and a conductive fill, but does disclose a conductive fill [110] In the same field of endeavor, Lee teaches wherein the plurality of conductive lines comprises a conductive barrier [108] and a conductive fill [110] (see Figure 2). Implementation of a conductive barrier of Lee within the conductive line structure of the combination of Jin and Xie serves as a diffusion barrier and seed layer for the conductive fill (See ¶[0042]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 3, the combination of Jin and Xie fails to disclose wherein the ILD structure is on a dielectric hardmask layer. In the same field of endeavor, Lee teaches wherein the ILD structure is on a dielectric hardmask layer [102] (see Figure 2). Implementation of a dielectric hardmask layer as taught by Lee within the device of the combination of Jin and Xie allows for an etch stop layer during processing of the device (see Lee ¶[0046]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 4, the combination of Jin, Xie and Lee discloses wherein the dielectric hardmask layer extends laterally beyond the bottom of the dielectric plug portion of the ILD structure (See Lee Figure 2).
With respect to claim 6, the combination of Jin, Xie and Lee discloses wherein the dielectric hardmask layer comprises silicon, nitrogen and oxygen (See ¶[0038]).
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jin and Xie
With respect to claim 11, Lee discloses a computing device [1000], comprising: a board [1002]; and a component coupled to the board (See Figure 25). Lee fails to disclose the component including an integrated circuit structure, comprising: a plurality of conductive lines along a same direction, one of the conductive lines having a break therein; and an inter-layer dielectric (ILD) structure having portions between adjacent ones of the plurality of conductive lines and having a dielectric plug portion in a location of the break in the one of the conductive lines, the dielectric plug portion of the ILD structure continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines, and the dielectric plug portion of the ILD structure having an inwardly tapering profile from top to bottom.
In the same field of endeavor, Jin discloses a plurality of conductive lines [110] along a same direction, one of the conductive lines having a break therein (see Figure 14); and an inter-layer dielectric (ILD) structure [101] having portions between adjacent ones of the plurality of conductive lines and having a dielectric plug portion [120] in a location of the break in the one of the conductive lines, the dielectric plug portion of the ILD structure continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines (see Figure 14 and ¶[0025] and ¶[0036]; no space is between [120] and [101] and both structures are formed of the same materials, therefore considered continuous), and a slightly tapered bottom (see Figure 15). Additionally within the same field of endeavor, Xie teaches the dielectric plug portion [702] of the ILD structure having an inwardly tapering profile from top to bottom (see Figure 9). Implementation of Jin’s ILD structure allows for segmentation of conductive lines to produce via interconnection structures to meet design requirements (see Jin ¶[0032]). Furthermore, the inward tapering profile of Xie’s dielectric plug portion within Jin’s already bottom tapered dielectric plug portion allows for a more precise minimum feature size and minimum pitch while providing the proper electrical isolation between the conductive regions (see Xie ¶[0032]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 12, the combination of Lee, Jin and Xie discloses a memory coupled to the board (See Lee Figure 25).
With respect to claim 13, the combination of Lee, Jin and Xie discloses a communication chip [1006] coupled to the board.
With respect to claim 14, the combination of Lee, Jin and Xie discloses a camera coupled to the board (See Lee Figure 25).
With respect to claim 15, the combination of Lee, Jin and Xie discloses wherein the component is a packaged integrated circuit die (See Figure 24-25; interconnect structures are within the logic and memory dies of the components).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7-10 and 16-20 are allowed.
With respect to claim 5, none of the prior art teaches or suggests, alone or in combination, wherein the dielectric plug portion of the ILD structure is on a portion of the dielectric hardmask layer having a first thickness, the portions of the ILD structure between adjacent ones of the plurality of conductive lines are on a portion of the dielectric hardmask layer having a second thickness, the second thickness greater than the first thickness.
With respect to claims 7-10, none of the prior art teaches or suggests, alone or in combination, an integrated circuit structure, comprising: wherein the dielectric plug portion of the ILD structure is on a portion of the dielectric hardmask layer having a first thickness, and the portions of the ILD structure between adjacent ones of the plurality of conductive lines are on a portion of the dielectric hardmask layer having a second thickness, the second thickness greater than the first thickness.
With respect to claims 16-20, none of the prior art teaches or suggests, alone or in combination, a computing device, comprising: wherein the dielectric plug portion of the ILD structure is on a portion of the dielectric hardmask layer having a first thickness, and the portions of the ILD structure between adjacent ones of the plurality of conductive lines are on a portion of the dielectric hardmask layer having a second thickness, the second thickness greater than the first thickness.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Yang et al. (U.S. Publication No. 2015/0371939 A1) discloses an interconnect structure with dielectric plugs but fails to disclose wherein the dielectric plug portion of the ILD structure is on a portion of the dielectric hardmask layer having a first thickness, and the portions of the ILD structure between adjacent ones of the plurality of conductive lines are on a portion of the dielectric hardmask layer having a second thickness, the second thickness greater than the first thickness. - Wang et al. (U.S. Patent No. 10,192,780 B1) discloses an interconnect structure with dielectric plugs but fails to disclose wherein the dielectric plug portion of the ILD structure is on a portion of the dielectric hardmask layer having a first thickness, and the portions of the ILD structure between adjacent ones of the plurality of conductive lines are on a portion of the dielectric hardmask layer having a second thickness, the second thickness greater than the first thickness.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818