DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 12/29/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 15, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication No. 2021/0020636).
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Regarding claim 1, Lee discloses an integrated circuit comprising: a semiconductor body Fig 1 or Fig 3, F1-F4 extending in a first direction from a source region to a drain region Fig 1-3 ;a gate structure Fig 1 or Fig 3, G1-G6 ¶0042 extending in a second direction over the semiconductor body Fig 1; and a first gate cut Fig 10B or 10C, CT2 ¶0052-0054 comprising a dielectric material and extending through an entire thickness of the gate structure in a third direction¶0046-0047, the first gate cut having a first width at a top surface of the gate structure Fig 10B or 10C, and a second width at a bottom surface of the gate structure Fig 10B or 10C, the first width greater than the second width Fig 10B or 10C, and the first gate cut having a first height that extends from an uppermost surface of the first gate cut to a lowermost surface of the first gate cut Fig 10B or 10C; and a second gate cut Fig 10B or 10C, CT1 comprising the dielectric material and extending through an entire thickness of the gate structure in the third direction ¶0046-0047, the gate cut having a third width at a top surface of the gate structure Fig 10B or 10C, and a fourth width at a bottom surface of the gate structure Fig 10B or 10C, the third width being greater than the fourth width Fig 10B or 10C, and the second gate cut having a second height that extends from an uppermost surface of the second gate cut to a lowermost surface of the second gate cut Fig 10C, the second height being lower than the first height Fig 10C or Fig 12B. Lee discloses all the limitations except for the specific width and the specific height difference. Lee discloses the claimed invention except for specific width. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the specific height and width difference, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 4, Lee discloses wherein the gate structure includes a gate dielectric around the semiconductor body, and wherein the gate dielectric Fig 12B, 224 is not present on any sidewall of the first gate cut and the second gate cut ¶0068-0069.
Regarding claim 5, Lee discloses all the limitations but silent on the width of the gate cut. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the specific width difference, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 6, Lee discloses all the limitations but silent on the aspect ratio of the gate cut. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the aspect ratio, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 15, Lee discloses an integrated circuit comprising: a first semiconductor region Fig 1 or Fig 3, F1-F4 extending in a first direction from a first source region to a first drain region Fig 1-3;a first gate structure Fig 1 or Fig 3, G1-G6 ¶0042 extending in a second direction over the first semiconductor region Fig 1 or Fig 3;a second semiconductor region Fig 1 or Fig 3, F1-F4 extending in the first direction from a second source region to a second drain region Fig 1 or Fig 3;a second gate structure Fig 1 or Fig 3, G1-G6 ¶0042 extending in the second direction over the second semiconductor region; and a gate cut Fig 10B or 10C, CT2 ¶0052-0054 directly between the first gate structure and the second gate structure Fig 1 or Fig 3, Fig 10B, Fig 12B, the gate cut comprising a dielectric material ¶0046-0047 and having a height Fig 10B, Fig 12B, and a width at a bottom surface of the first gate structure and the second gate structure Fig 10B, Fig 12B. Lee discloses the claimed invention except for specific width and height. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the specific height and width , since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 18, Lee discloses wherein the first gate structure includes a first gate dielectric Fig 12B, 224 around the first semiconductor region, and the second gate structure includes a second gate dielectric Fig 12B, 224 around the second semiconductor region¶0068-0069.
Regarding claim 19, Lee discloses wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut Fig 12B ¶0068-0069.
Regarding claim 20, Lee discloses wherein the gate cut has a first width at a top surface of the first gate structure and the second gate structure, and the width at the bottom surface of the first gate structure and the second gate structure is a second width Fig 11C and Fig 12B. Lee discloses the claimed invention except for specific width of the gate cut. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the specific width of the top and bottom of the gate cut , since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Claims 2-3, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication No. 2021/0020636) in view of Wu et al (US Publication No. 2023/0015372).
Regarding claims 2 and 16, Lee discloses all the limitations but silent on the dielectric liner. Whereas Wu discloses wherein each of the first and second gate cuts comprises a dielectric layer along one or more edges of the gate cut and a dielectric fill in a remaining volume of the gate cut Fig 10B ¶0031-0033. Lee and Wu are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the gate cut of Lee and incorporate the teachings of Wu to improve device isolation.
Regarding claims 3 and 17, Lee discloses all the limitations but silent on the type of channel region. Whereas Wu discloses wherein the semiconductor body comprises a plurality of semiconductor nanoribbons Fig 14C. Lee and Wu are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the channel of Lee and incorporate the teachings of Wu as an alternative channel type known in the art as a matter of design choice.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication No. 2021/0020636) in view of Wei et al (US Publication No. 2021/0280708).
Regarding claim 7, Lee discloses all the limitations but silent on the printed circuit board. Whereas Wei discloses a printed circuit board comprising an integrated circuit containing a device with a gate cut Fig 7D, Fig 9-10 ¶0107-0110. Lee and Wei are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lee and incorporate the teachings of Wei to provide and integrated circuit.
Claims 21, 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (US Publication No. 2021/0280708) in view of Lee et al (US Publication No. 2021/0020636).
Regarding claim 21, Wei discloses an electronic device comprising: a chip package having one or more dies Fig 9-10, at least one of the one or more dies comprising a semiconductor body Fig 5A, 104 extending in a first direction from a source region to a drain region Fig 5A;a gate structure Fig 5A, 212 extending in a second direction over the semiconductor body Fig 5A; and a gate cut Fig 5A, 312-2 comprising a dielectric material ¶0078, 0092-0093 and extending through an entire thickness of the gate structure in a third direction Fig 5A. Wei discloses all the limitations but silent on the width of the gate cut. Whereas Lee a gate cut Fig 10B or 10C, CT2 ¶0052-0054 directly between the first gate structure and the second gate structure Fig 1 or Fig 3, Fig 10B, Fig 12B, the gate cut comprising a dielectric material ¶0046-0047 and having a height Fig 10B, Fig 12B, and a width at a bottom surface of the first gate structure and the second gate structure Fig 10B, Fig 12B; wherein the gate cut has a first width at a top surface of the gate structure and a second width at a bottom surface of the gate structure Fig 10B, Fig 12B. Wei and Lee are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the shape of the gate cut and incorporate the teachings of Lee since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Lee discloses the claimed invention except for specific width. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the top surface width is at most 10% greater than the bottom width, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 24, Lee discloses wherein the gate structure includes a gate dielectric around the semiconductor body, and wherein the gate dielectric Fig 12B, 224 is not present on any sidewall of the first gate cut and the second gate cut ¶0068-0069.
Regarding claim 25, Lee discloses all the limitations but silent on the width of the gate cut. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the specific width difference, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 26, Lee discloses all the limitations but silent on the aspect ratio of the gate cut. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the aspect ratio, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 27, Lee discloses all the limitations but silent on the height of the gate cut. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the specific width difference, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966).
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (US Publication No. 2021/0280708) in view of Lee et al (US Publication No. 2021/0020636) and in further view of Wu et al (US Publication No. 2023/0015372).
Regarding claim 22, Wei and Lee discloses all the limitations but silent on the dielectric liner. Whereas Wu discloses wherein the gate cut comprises a dielectric layer along one or more edges of the gate cut and a dielectric fill in a remaining volume of the gate cut Fig 10B ¶0031-0033.Wei, Lee and Wu are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wei because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the gate cut of Wei and incorporate the teachings of Wu to improve device isolation.
Regarding claim 23, Wu discloses wherein the dielectric layer comprises a high-k dielectric material¶0031-0033.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811