DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 05/18/2026 has been accepted and entered. Claims 1-22 remain pending in this application. Applicant’s amendments to the Specification, Drawing, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed on 03/22/2026.
Election/Restrictions
Claims 16-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/07/2026.
Claims 1-15 are still pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20110136295 A1-Sakai95) from IDS, in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15).
Regarding claim 1, Sakai95 discloses a semiconductor device (image device has been interpretated as a semiconductor device-Abstract L1)comprising:
one or more substrate layers (Substrate layers 61/62/63 of substrate 60-Fig 2D);
an electrical circuitry in at least one of the one or more substrate layers (Photodiode 21 and transfer gate 23 have been interpretated as the electrical circuit in the substrate layer 63-Fig 2B) ; and
a cavity in the metal routing of the electrical circuitry (Cavity 16 in metal routing 31 of the electrical circuitry 21/23-Fig 2E).
Sakai95 does not disclose a semiconductor device comprising:
a nano-bubble
NPLNanda15 teaches a semiconductor device comprising:
a nano-bubble (nano-bubble as beam induced defect-Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Sakai95 as taught byNPLNanda15 for the purpose of optimizing controlled modification and minimizing collateral damage (NPLNanda15: p4006, C1 L30-C2 L2).
Regarding claim 2, Sakai95 and NPLNanda15 combination discloses all the elements of claim 1, as noted above.
Sakai95 further discloses a semiconductor device
further comprising a plurality of ion atoms proximate to the cavity (Hydrogen ion implementation having at least two ion atoms is done in the cavity 90 so a plurality of ion atoms proximate the cavity 90-Fig 4C).
Regarding claim 3, Sakai95 and NPLNanda15 combination discloses all the elements of claim 2, as noted above.
Sakai95 further discloses a semiconductor device
wherein the plurality of ion atoms include a selected one or more of. helium, lithium, hydrogen, argon, nitrogen, oxygen, silicon, boron, carbon, argon, or neon atoms (Hydrogen ion implementation having at least two ion atoms is done in the cavity 90 so a plurality of ion atoms proximate the cavity 90-Fig 4C).
Regarding claim 4, Sakai95 and NPLNanda15 combination discloses all the elements of claim 1, as noted above.
Sakai95 further discloses a semiconductor device
wherein the cavity is proximate to a dielectric layer (Cavity 90 proximate to dielectric layer 31, Dielectric layer 31 having an interlayer insulating film 33 so dielectric-Fig 4C, [0068]).
Regarding claim 5, Sakai95 and NPLNanda15 combination discloses all the elements of claim 1, as noted above.
Sakai95 further discloses a semiconductor device
wherein the cavity is at least partially filled with implanted ions (Hydrogen ion implementation having at least two ion atoms is done in the cavity 90 so a plurality of ion atoms at least partially fills the cavity 90-Fig 4C).
Regarding claim 6, Sakai95 and NPLNanda15 combination discloses all the elements of claim 1, as noted above.
Sakai95 further discloses a semiconductor device
wherein the electrical circuitry includes a selected one or more of:
a metal routing or
a portion of a transistor structure (Photodiode 21 and transfer gate 23 have been interpretated as the electrical circuit in the substrate layer 63 so the electrical circuitry 21/23 includes a portion of a transistor structure 23-Fig 2B).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20110136295 A1-Sakai95) from IDS, in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zou et al. (US20220037481 A1-Zou81) from IDS.
Regarding claim 7, Sakai95 and NPLNanda15 combination discloses all the elements of claim 1, as noted above.
Sakai95 and NPLNanda15 combination does not disclose a semiconductor device
wherein the cavity electrically isolates a first part of the electrical circuitry from a second part of the electrical circuitry.
Zou81 teaches a semiconductor device
wherein the cavity electrically isolates a first part of the electrical circuitry from a second part of the electrical circuitry (Cavity 170 separating the three left word lines 190 from the three right word lines so electrically separating a first part of the electrical circuitry 190 to a second part of the electrical circuitry 190-Examiner's annotated Fig 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Sakai95 in view of NPLNanda15, as taught by Zou81for the purpose of avoiding deterioration in performance of the transistor caused by depth variation of the gate groove (Zou81:[0005]).
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Regarding claim 8, Sakai95 and NPLNanda15 combination discloses all the elements of claim 1, as noted above.
Sakai95 and NPLNanda15 combination does not disclose a semiconductor device wherein the semiconductor device has
a first side and
a second side opposite the first side, and
wherein the cavity has a distance from the first side or the second side that is greater than 100 nm.
Zou81 teaches a semiconductor device wherein the semiconductor device has
a first side (Examiner's annotated Fig 10) and
a second side opposite the first side (Examiner's annotated Fig 10), and
wherein the cavity has a distance from the first side or the second side that is greater than 100 nm (the distance from second side is larger than the depth of the gate groove h, which is in average 137.5nm, so the distance is greater than 100nm-Fig 10, Fig 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Sakai95 in view of NPLNanda15, as taught by Zou81for the purpose of avoiding deterioration in performance of the transistor caused by depth variation of the gate groove (Zou81:[0005]).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), and further in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15).
Regarding claim 9, Amoroso84 discloses a semiconductor device (integrated circuit-Abstract) comprising:
one or more substrate layers (Substrate layer 205-Fig 2);
a transistor structure within the one or more substrate layers (FinFET transistor within substrate 205-Fig 5F, [0012]) ,
wherein the transistor structure includes
a source (source255-Fig 2),
a channel (Channel 160-Fig 1C) , and
a drain (Drain 255-Fig 2); and
wherein a first location within the channel includes a material with a first crystalline structure or a first amorphous structure (ion implementation is done with an angle 145a, then 145b; after the both of the ion implantations, the left side of the silicon fin 160 of the substrate 105, so in the first location, has a first structure of silicon/silicon dioxide different, so having a first crystalline structure or first amorphous structure-Fig 4A, Fig 4B, [0030], [0005]), and
wherein a second location within the channel includes the material with a second crystalline structure or a second amorphous structure (ion implementation is done with an angle 145a, then 145b; after the ion implantations, the right side of the fin 160 of the substrate 105, so in the second location, has a second structure of silicon/silicon dioxide, so having a second crystalline structure or second amorphous structure-Fig 4A, Fig 4B, [0030], [0005]).
Amoroso84 does not explicitly disclose a semiconductor device
wherein the first crystalline structure or the first amorphous structure is different than the second crystalline structure or the second amorphous structure and
has a nano-bubble therein.
Majhi36 teaches a semiconductor device
wherein the first crystalline structure or the first amorphous structure is different than the second crystalline structure or the second amorphous structure (the first crystalline or the first amorphous structure 297/298 is different than second crystalline structure or the second amorphous structure 299 after two or more angled ion implantations-Fig 3F, Fig 3G, [0065] L10-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Amoroso84, as taught by Majhi36 for the purpose of enabling the fabrication of higher effective widths for a transistor for a scaled (reduced) projected area. Accordingly, the drive strength and performance of such transistors may be improved (Majhi36:[0029]).
Majhi36 does not explicitly disclose a semiconductor device
wherein the first crystalline structure or the first amorphous structure
has a nano-bubble therein.
NPLNanda15 teaches a semiconductor device
wherein the first crystalline structure or the first amorphous structure
has a nano-bubble therein (nano-bubble as beam induced defect in the first crystalline structure graphene-Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Amoroso84in view of Majhi36, as taught byNPLNanda15 for the purpose of optimizing controlled modification and minimizing collateral damage (NPLNanda15: p4006, C1 L30-C2 L2).
Regarding claim 10, Amoroso84, Mahji36, and NPLNanda15 combination discloses all the elements of claim 9, as noted above.
Amoroso84 further discloses a semiconductor device
further comprising a plurality of ions proximate to the second crystalline structure (ion implementation is done with an angle 145a, then 145b; after the first ion implantation, the side of the fin 160 of the substrate 105 facing the ion implementation 145a, so in the first location, has some oxygen ions in the first location so proximate to the second crystalline structure -Fig 4A, Fig 4B, [0030]).
Regarding claim 11, Amoroso84, Mahji36, and NPLNanda15 combination discloses all the elements of claim 10, as noted above.
Amoroso84 further discloses a semiconductor device
wherein the plurality of ions include a selected one or more of: include a selected one or more of: helium, lithium, hydrogen, argon, nitrogen, oxygen, silicon, boron, carbon, argon, or neon ions (Oxygen ions-[0006]).
Regarding claim 12, Amoroso84, Mahji36, and NPLNanda15 combination discloses all the elements of claim 9, as noted above.
Amoroso84 further discloses a semiconductor device
wherein the second crystalline structure or the second amorphous structure is formed using a focused ion beam ([0005]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zani et al. (US 20070045534 A1-Zani34).
Regarding claim 13, Amoroso84, Mahji36, and NPLNanda15 combination discloses all the elements of claim 9, as noted above.
Amoroso84, Mahji36, and NPLNanda15 combination does not disclose a semiconductor device
wherein the second crystalline structure or the second amorphous structure alters a timing of the transistor structure.
Zani34 teaches a semiconductor device
wherein the second crystalline structure or the second amorphous structure alters a timing of the transistor structure (beam implementation can reduce stray capacitance and improves operating frequency so timing by reducing junction capacitance-[0155] L6-8, L9-19, [0156] L3-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Amoroso84 in view of Majhi36, and further in view of NPLNanda15, as taught by Zani34 for the purpose of reducing stray capacitance and improves the operating frequency (Zani34:[0155] L9-19).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zou et al. (US20220037481 A1-Zou81).
Regarding claim 14, Amoroso84, Mahji36, and NPLNanda15 combination discloses all the elements of claim 9, as noted above.
Amoroso84, Mahji36, and NPLNanda15 combination does not disclose a semiconductor device
wherein the second crystalline structure or the second amorphous structure alters a threshold voltage (Vt) of the transistor structure.
Zou81 teaches a semiconductor device
wherein the second crystalline structure or the second amorphous structure alters a threshold voltage (Vt) of the transistor structure (beam implementation can control the density of moveable charges so enhances the threshold voltage, so altering the threshold voltage-[0036] L 4-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Amoroso84 in view of Majhi36, and further in view of NPLNanda15, as taught by Zou81 for the purpose of avoiding deterioration of performance of the semiconductor structure caused by variation in the depth h of the gate groove (Zou81:[0036]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Sakai et al. (US 20110136295 A1-Sakai95) from IDS.
Regarding claim 15, Amoroso84, Mahji36, and NPLNanda15 combination discloses all the elements of claim 9, as noted above.
Amoroso84, Mahji36, and NPLNanda15 combination does not disclose a semiconductor device further comprising:
a first plurality of metal layers on a first side of the transistor structure; and
a second plurality of metal layers on a second side of the transistor structure opposite the first side of the transistor structure.
Sakai95 teaches a semiconductor device further comprising:
a first plurality of metal layers on a first side of the transistor structure (Wiring 131 on the vertical right sidewall of transistor structure 1-Fig 6); and
a second plurality of metal layers on a second side of the transistor structure opposite the first side of the transistor structure (Wiring 131 on the vertical Left sidewall of transistor structure 1, Left vertical sidewall being opposite to right vertical sidewall-Fig 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Amoroso84 in view of Majhi36, and further in view of NPLNanda15, as taught by Sakai95 for the purpose of improving the metal contamination level, so that the level of dark current/white spots can be improve (Sakai95: [0132]).
Response to Arguments
Applicant’s arguments see pages 7-11 of Remarks, filed on 05/18/2026 with respect to claim(s) 1 102 rejection and claim 9 103 rejection, have been considered.
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claims 1 and 9 have been amended to further define the claimed subject matter see pages 4-7 of Amendments to Claims, filed on 5/12/2025.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20110136295 A1-Sakai95) from IDS, in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), as described above.
Therefore, claim(s) 1-6 stand rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20110136295 A1-Sakai95) from IDS, in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20110136295 A1-Sakai95) from IDS, in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zou et al. (US20220037481 A1-Zou81) from IDS, as described above.
Therefore, claim(s) 7-8 stand rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20110136295 A1-Sakai95) from IDS, in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zou et al. (US20220037481 A1-Zou81) from IDS.
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), and further in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), as described above.
Therefore, claim(s) 9-12 stand rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), and further in view Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zani et al. (US 20070045534 A1-Zani34), as described above.
Therefore, claim(s) 13 stand rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zani et al. (US 20070045534 A1-Zani34).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zou et al. (US20220037481 A1-Zou81), as described above
Therefore, claim(s) 14 stands rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Zou et al. (US20220037481 A1-Zou81).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Sakai et al. (US 20110136295 A1-Sakai95) from IDS, as described above.
Therefore, claim(s) 15 stands rejected under 35 U.S.C. 103 as being unpatentable over Amoroso et al. (US20220302284A1-Amoroso84) in view of Majhi et al. (US 20200168636 A1-Majhi36), in view of Nanda et al. ( Nano Lett. 2015, 15, 6, 4006–4012-NPLNanda15), and further in view of Sakai et al. (US 20110136295 A1-Sakai95) from IDS.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 06/01/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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