DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant’s Arguments
Applicant argues that Takahashi does not disclose “generating x-rays using the x-ray generation source, wherein the generated x-rays pass through the identified location within the semiconductor device and alter the semiconductor device proximate to the identified location,” as recited in independent claim 1. Applicant asserts that Takahashi merely performs structural analysis and does not disclose alteration of the semiconductor device.
The Examiner respectfully disagrees.
Takahashi discloses subjecting a semiconductor film to structural analysis using an X-ray diffraction (XRD) apparatus (Takahashi para 0334). Takahashi further explains that the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters the sample in a direction substantially perpendicular to the c-axis (Takahashi para 0335). Thus. Takashi clearly teaches generating X-rays and directing those X-rays into a semiconductor material for analysis.
In performing X-ray diffraction analysis, the generated X-rays necessarily penetrate the semiconductor material and interact with the crystal lattice of the semiconductor. This interaction results in scattering and diffraction of the X-rays by atoms within the semiconductor lattice. Such interaction inherently involves energy transfer between the X-rays and the semiconductor material at or proximate of the irradiated location, even if such alteration is temporary or occurs at the atomic level.
The claims do not require that the alteration be permanent or that the semiconductor device be structurally modified in a lasting manner. Rather, the claims merely require that the generated X-rays pass through the identified location within the semiconductor device and alter the semiconductor device proximate to the identified location. The interaction between the generated X-rays and the semiconductor lattice during the X-ray diffraction necessarily satisfies these limitations.
Accordingly, Takashashi teaches generating X-rays that pass through a location within the semiconductor device and inherently alter the semiconductor device proximate to the irradiated location. Therefore, the rejection as being anticipated by Takahashi is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi et al. (U.S. Publication No. 2016/0195584 A1).
With respect to claim 1, Takahashi et al. discloses a method comprising:
providing an x-ray generation source (para 0341, lines 1-5);
providing a semiconductor device (para 0008, lines 1-11);
identifying a location within the semiconductor device (para 0394, lines 1-9); and
generating x-rays using the x-ray generation source, wherein the generated x-rays pass through the identified location within the semiconductor device and alter the semiconductor device proximate to the identified location (para 0401, lines 1-4).
With respect to claim 2, Takahashi et al. discloses the method of claim 1, wherein to alter the semiconductor device proximate to the identified location further includes to change an operational characteristic of the semiconductor device (para 0034, lines 1-9).
With respect to claim 3, Takahashi et al. discloses the method of claim 1, wherein generating x-rays using the x-ray generation source further includes generating x-rays while the semiconductor device is undergoing operational testing (para 0008, lines 1-11).
With respect to claim 4, Takahashi et al. discloses the method of claim 3, wherein undergoing operational testing further includes a selected one or more of: observing a current or observing a voltage state of the semiconductor device (para 0010, lines 3-9).
With respect to claim 5, Takahashi et al. discloses the method of claim 3, wherein generating x-rays using the x-ray generation source further comprises synchronizing generating x-rays with the operational testing of the semiconductor device (para 0013, lines 1-6).
With respect to claim 6, Takahashi et al. discloses the method of claim 1, wherein the semiconductor device includes one or more metal layers between the identified location and the x-ray generation source (para 0034, lines 1-9).
With respect to claim 7, Takahashi et al. discloses a system for testing a semiconductor device (para 0013, lines 1-5), the system comprising:
an x-ray tool, the x-ray tool including a source for generating x-rays (para 0008, lines 1-6);
a holder, wherein the holder is coupled with the semiconductor device (para 0013, lines 1-6); and
a controller [721] (see Fig. 10), wherein the controller is electrically coupled with the x-ray tool and the holder, and wherein the controller is configured to position an x-ray beam generated by the x-ray tool with respect to a target location within the semiconductor device (para 0190, lines 1-3), the generated x-ray beam configured to pass through the target location within the semiconductor device and alter the semiconductor device proximate to the target location (para 0401, lines 1-4).
With respect to claim 8, Takahashi et al. discloses the system of claim 7, wherein the holder is electrically coupled with the semiconductor device (para 0198, 1-5).
With respect to claim 9, Takahashi et al. discloses the system of claim 8, wherein the controller is configured to synchronize generation of x-rays on the target location within the semiconductor device with an electrical operation of the semiconductor device (para 0190, lines 1-3).
With respect to claim 10, Takahashi et al. discloses the system of claim 9, wherein the controller is configured to receive operational data from the semiconductor device (para 0008, lines 1-6).
With respect to claim 11, Takahashi et al. discloses the system of claim 7, wherein the x-ray tool further includes a camera; and wherein a positioning of the semiconductor device is based at least in part on an output of the camera (para 0200, lines 1-7).
With respect to claim 12, Takahashi et al. discloses the system of claim 11, wherein the camera includes a selected one or more of: a fluorescence detector or a near infrared (NIR) microscope (para 0328, lines 1-5).
With respect to claim 13, Takahashi et al. discloses the system of claim 7, further comprising a shield that surrounds at least a portion of the x-ray tool and the holder (para 0325, lines 1-8).
With respect to claim 14, Takahashi et al. discloses the system of claim 7, further comprising a cooling system that is thermally coupled with the holder and with the semiconductor device (para 0334, lines 1-10).
With respect to claim 15, Takahashi et al. discloses the system of claim 7, wherein the holder further includes a clamp (para 0150, lines 1-4).
With respect to claim 16, Takahashi et al. discloses an apparatus comprising:
a source for generating x-rays (para 0325, lines 1-8);
a target location for the x-rays generated by the source (para 0158, lines 1-8); the target location within a semiconductor device, and the generated x-rays configured to pass through the target location within the semiconductor device and alter the semiconductor device proximate to the target location (para 0401, lines 1-4) a layer between the source and the target location (para 0162, lines 1-4); and an aperture in the layer, wherein the aperture extends from a first side of the layer to a second side of the layer opposite the first side (para 0162, lines 1-8), and wherein the aperture is between the source and the target location (para 0178, lines 1-6).
With respect to claim 17, Takahashi et al. discloses the apparatus of claim 16, wherein a diameter of the aperture is determined based upon a distance between the layer and the target location (para 0182, lines 1-6).
With respect to claim 18, Takahashi et al. discloses the apparatus of claim 16, wherein the layer is opaque (para 0182, lines 1-5).
With respect to claim 19, Takahashi et al. discloses the apparatus of claim 16, wherein the aperture in the layer further includes a plurality of apertures in the layer, and wherein the layer is configured to rotate around an axis (para 0327, lines 1-2).
With respect to claim 20, Takahashi et al. discloses the apparatus of claim 16, wherein a diameter of the aperture ranges from 0.1um to 3.0 um (para 0338, lines 1-11).
With respect to claim 21, Takahashi et al. discloses the apparatus of claim 16, wherein the aperture is a selected one of: a circle, a rectangle, an oval, or a slit (para 0338, lines 1-11).
With respect to claim 22, Takahashi et al. discloses the apparatus of claim 16, further comprising optics between the source and the layer (para 0484, lines 10-18).
With respect to claim 23, Takahashi et al. discloses the apparatus of claim 22, wherein the optics include a selected one or more of: a mirror, a grating, a lens, and/or a Fresnel lens (para 0473, lines 8-11).
With respect to claim 24, Takahashi et al. discloses the apparatus of claim 16, wherein the target location is within a semiconductor device, and wherein the target location is a selected one or more of: a transistor layer or a metal layer (para 0503, lines 1-5).
With respect to claim 25, Takahashi et al. discloses the apparatus of claim 24, wherein the semiconductor device includes a first plurality of metal layers above the transistor layer and/or a second plurality of metal layers below the transistor layer (para 0503, lines 1-5).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARHANA AKHTER HOQUE whose telephone number is (571)270-7543. The examiner can normally be reached Monday-Friday, 7:30am-4:00pm.
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/FARHANA A HOQUE/Primary Examiner, Art Unit 2858