Prosecution Insights
Last updated: July 17, 2026
Application No. 17/952,161

VERTICAL FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES

Final Rejection §102§112
Filed
Sep 23, 2022
Examiner
RAHMAN, MOHAMMAD A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
480 granted / 553 resolved
+18.8% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
35 currently pending
Career history
580
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
63.0%
+23.0% vs TC avg
§102
17.9%
-22.1% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of Claims Applicant's amendment of claims 1, 9, 26 in “Claims - 05/06/2026” have been acknowledged. This office action considers claims 1-19, 26-31 pending for prosecution, and are examined on their merits. Response to Arguments Applicant's arguments “Remarks - 05/06/2026 - Applicant Arguments/Remarks Made in an Amendment”, have been fully considered, but they are not persuasive. Applicant argues with respect to claim 1 that Doyle does not disclose “first dielectric material on the substrate and adjacent the first source or drain material.” Examiner relied on Fig. 3G of Doyle (US 20200235244 A1) to reject claim 1. Examiner equated right bottom 210 as the first dielectric material, 202 as the substrate and 206 as the source or drain material. As is seen in Fig. 3G of Doyle, first dielectric material right bottom 210 is on 202 (with intervening layer 206) and is adjacent to the source or drain material 206. Applicant further argues that Doyle does not disclose “second dielectric material on the FE material and the gate material”. Examiner equated second dielectric material to Doyle’s top right 210 and top right 212 as the gate material and 218 and FE. Fig. 3G clearly shows the top right 210 is on 212 and 218. Fig. 3G also shows 210 is adjacent to second source or drain material 208. Therefore, the examiner respectfully contends that the rejection of claim 1 is proper. For the rejections of claims 5-8, applicant’s argument is persuasive and therefore, the rejections are withdrawn. Claim Objections withdrawn Claims 1-10, 26-31 were objected to because of informalities. Applicant’s amendments overcome this objection. Claim Rejections - 35 USC § 102 The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 1, 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Doyle et al. (US 20200235244 A1 – hereinafter Doyle). Regarding Claim 1, Doyle teaches a semiconductor device (see the entire document; Fig. 3G along with Figs. 3A-3F; specifically, ([0038] - [0044]), and as cited below), comprising: a substrate (202 – Fig. 3G – [0038]); a first source or drain material (206 – [0043]) on the substrate (202); a semiconductor material (222 – [0044] – also see Fig. 3F) on the first source or drain material (206); a second source or drain (208 – [0048]) material on the semiconductor material (222); a first dielectric material (right bottom 210 – [0042]) on the substrate (202) and adjacent the first source or drain material (206); a ferroelectric (FE) material (right 218 – [0042]) on the first dielectric material (right bottom 210) and adjacent the semiconductor material (222); a gate material (top right 212 – [0042]) on the on the first dielectric material (right bottom 210) and adjacent the FE material (right 218); and a second dielectric material (top right 210) on the FE material (right 218) and gate material (top right 212), the second dielectric material (top right 210) adjacent the second source or drain material (208). Regarding Claim 3, Doyle teaches the device of claim 1, wherein the FE material (218) is a perovskite material ([0047]). Regarding Claim 4, Doyle teaches the device of claim 1, wherein the FE material includes one or more of Barium, Titanium, Zirconium, Calcium, Strontium, Lanthanum, Bismuth, Iron, Cobalt, Lithium, Niobium, Potassium, and Oxygen ([0047]). Allowable Subject Matter Claims 2, 5-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s Reasons for Allowance: The prior art fails to disclose and would not have rendered obvious: Regarding claim 2: The device of claim 1, wherein a lattice parameter of the semiconductor material is higher than a lattice parameter of the FE material. Regarding claim 5: The device of claim 1, wherein the semiconductor material includes one or more of Barium, Tin, Lanthanum, Neodymium, Strontium, Titanium, Indium, Gallium, Zinc, Nickel, and Oxygen. Regarding claim 6: The device of claim 1, wherein the substrate comprises one or more of Strontium, Titanium, Gadolinium, Scandium, Dysprosium, Lanthanum, Aluminum, Barium, Hafnium, Zirconium, Indium, Lutetium, Magnesium, and Oxygen. Regarding claim 7: The device of claim 1, wherein the first source or drain material and the second source or drain material each comprise one or more of Strontium, Ruthenium, Barium, Lanthanum, Tin, Manganese, Cobalt, Nickel, Yttrium, Copper, Vanadium, Molybdenum, Platinum, Iridium, Palladium, Tungsten, and Oxygen. Regarding claim 8: The device of claim 1, wherein the gate material comprises one or more of Strontium, Ruthenium, Barium, Lanthanum, Tin, Manganese, Cobalt, Nickel, Yttrium, Copper, Vanadium, Molybdenum, Platinum, Iridium, Palladium, Tungsten, and Oxygen. Regarding claim 9: The device of claim 1, wherein the FE material is a first FE material and the gate material is a first gate material, and the device further comprises: a third dielectric material on the substrate and adjacent the first source or drain material; a second FE material on the third dielectric material and adjacent the semiconductor material; a second gate material on the on the third dielectric material and adjacent the second FE material; a fourth dielectric material on the second FE material and the second gate material, the fourth dielectric material adjacent the second source or drain material. Regarding claim 10: The device of claim 1, wherein the semiconductor material is a first semiconductor material, and the device further comprises: a third dielectric material on the second source or drain material; a third source or drain material on the third dielectric material; a second semiconductor material on the third source or drain material; a fourth source or drain material on the second semiconductor material; a second FE material on the second dielectric material and adjacent the second semiconductor material, wherein the gate material is further adjacent the second FE material; and a fourth dielectric material on the second FE material and the gate material. REASON FOR ALLOWANCE Claims 11-19, 26-31 are allowed over prior art. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). Regarding claim 11, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation). The most relevant prior art reference(s) (US 20200235244 A1 to Doyle) substantially teach(es) some of limitations in claim 11 as indicated in the rejection of claim1 above, but not the limitations of “wherein the FE material has a lattice parameter that is less than a lattice parameter of the semiconductor material” as recited in claim 11. Therefore, the claim 11 is deemed patentable over the prior art. Regarding claims 12-19, they are allowed due to their dependencies on claim 11. Regarding claim 26, similar to claim 11, Doyle teaches some the limitations of claim 26, but not the limitations of “a second dielectric material on the first FE material and first gate material, the second dielectric material adjacent the second source or drain material; a third dielectric material on the substrate and adjacent the first source or drain material; a second FE material on the third dielectric material and adjacent the semiconductor material; a second gate material on the on the third dielectric material and adjacent the second FE material; a fourth dielectric material on the second FE material and the second gate material, the fourth dielectric material adjacent the second source or drain material” as recited in claim 11. Therefore, the claim 11 is deemed patentable over the prior art. Regarding claims 27-31, they are allowed due to their dependencies on claim 16. Conclusion THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Sep 23, 2022
Application Filed
Apr 20, 2023
Response after Non-Final Action
Feb 06, 2026
Non-Final Rejection mailed — §102, §112
May 06, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685134
LOCAL FRONTSIDE POWER RAIL WITH GLOBAL BACKSIDE POWER DELIVERY
3y 9m to grant Granted Jul 14, 2026
Patent 12684842
POWER SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
3y 7m to grant Granted Jul 14, 2026
Patent 12684907
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 6m to grant Granted Jul 14, 2026
Patent 12677530
DISPLAY PANEL AND EVAPORATION METHOD FOR DISPLAY PANEL
3y 4m to grant Granted Jul 07, 2026
Patent 12677473
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
2y 12m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+11.1%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month