DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed September 17, 2025 has been entered. Applicant' s amendments to the Specification and Drawings have overcome each and every objection set forth in the Non-Final Office Action mailed July 16, 2025
Claims 1, 3-8, and 10-17 remain pending in the application.
Response to Arguments
Applicant’s arguments with respect to claims 8, 10-14 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 8, 10-12, and 17 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Burns, Jr.; Stuart Mcallister et al. (US 6013548; hereinafter Burns).
Regarding claim 8, Burns discloses a semiconductor structure (in particular, Figs 27-33; Col 16, line 5 – Col 17, line 13; Col 17, line 51 - Col 18, line 18; entire document) comprising:
a substrate (235; Figs 27-28; Col 16, line 50), the substrate being internally provided with a first isolation trench (bitline trench 210; Figs 27-28; Col 16, lines 22-23) and a second isolation trench (wordline trench 430; Figs 27-28; Col 16, lines 19-21), the first isolation trench and the second isolation trench being configured to isolate a plurality of active pillars (comprising 230,240,402; Figs 27-28; Col 17, line 6 - Col 17, line 13) arranged at intervals, the first isolation trench extending along a first direction (bitline direction; Fig 28), the second isolation trench extending along a second direction (wordline direction; Fig 28), the first direction intersecting with the second direction, a width (F plus Delta; Fig 28; Col 18, line 1-4; Col 6, lines 33-38) of the second isolation trench being greater than a width (F; Fig 28; Col 18, line 1-4; Col 6, lines 33-38) of the first isolation trench, and each of the plurality of active pillars comprising a first connection terminal (source 405; Figs 27-28,30-33; Col 16, lines 45-50), a second connection terminal (drain 240; Figs 27-28,31-33; Col 16, lines 27-30), and a channel region (230; Figs 28-33; Col 8, lines 22-31) positioned between the first connection terminal and the second connection terminal;
a first isolation dielectric layer (250 along 210; Fig 9; Col 8, lines 39-42; Col 16, lines 54-59) positioned in the first isolation trench;
a second isolation dielectric layer (250 along 430, between pillars 230 in wordline direction; Fig 9; Col 16, lines 54-59) positioned in the second isolation trench, the second isolation dielectric layer and the first isolation dielectric layer being configured to jointly wrap the first connection terminal of each of the plurality of active pillars (as shown in Fig 9), and the second isolation dielectric layer and the first isolation dielectric layer exposing the second connection terminal (as shown in Fig 9);
a plurality of word line structures (275,270; Figs 27, 31-33; Col 16, lines 16-17; Col 8, lines 42-44) arranged at intervals, the plurality of word line structures all extending along the second direction to wrap the channel regions of the plurality of active pillars positioned in a same row (Fig 27); and
a protective layer (245,270; Figs 28-33; Col 16, lines 27-28,58-61), the protective layer surrounding the second connection terminal of each of the plurality of active pillars;
a plurality of bit lines (220 {405,n+source}; Figs 28{405}, 32{n+source}; Col 16, lines 21-23) arranged at intervals, the plurality of bit lines being positioned below the plurality of active pillars (as shown in Figs 28,32) the plurality of bit lines all extending along the first direction to sequentially connect in series the first connection terminals of the plurality of active pillars positioned in a same column(as shown in Figs 28,32), the plurality of bit lines are located between a bottom of the first connection terminals of the plurality of active pillars and the substrate (as shown in Figs 28,32).
Regarding claim 10, Burns discloses the semiconductor structure according to claim 8, wherein a width of the second isolation trench (F plus Delta {as applied to claim 1}, where Delta is approximately 0.2F; Col 8, lines 34-38) is 1.2 times to 1.8 times a width (F {as applied to claim 1}) of the first isolation trench.
Regarding claim 11, Burns discloses the semiconductor structure according to claim 8, wherein the plurality of word line structures (275,270; Figs 27, 31-33) comprise:
gate dielectric layers (270; Figs 27, 31-33; Col 16, lines 16-17,59), positioned on surfaces of the channel regions and configured to wrap the channel regions; and
word line conductive layers (275; Figs 27, 31-33; Col 16, lines 16-17; Col 8, lines 42-44) positioned on surfaces of the gate dielectric layers and extending along the second direction (as shown in Fig 27), the word line conductive layers being configured to wrap the channel regions of the plurality of active pillars positioned in the same row (as shown in Fig 27).
Regarding claim 12, Burns discloses the semiconductor structure according to claim 8, wherein the protective layer comprises a patterned mask layer (245; Figs 13-14,28-30; Col 9, lines 39-62; Col 16, lines 27-28) the patterned mask layer being positioned at a top of each of the second connection terminals (240) and extending along the first direction.
Regarding claim 17, Burns discloses a storage structure (Fig 33, comprising the structure 520 of Fig 35 {where Fig 35 an example design for structure 520 of Fig 33; Col 18, lines 19-26}; Col 16, line 5 – Col 19, line 44; entire document), comprising:
the semiconductor structure according to claim 8;
a plurality of storage node structures (525; Fig 35; Col 18, line 60 – Col 19, line 5), the plurality of storage node structures being positioned above the second connection terminals (240; Figs 33,35) of the plurality of active pillars, and being connected in one-to-one correspondence to the second connection terminals (Col 19, lines 12-19); and
a plurality of capacitors (525,530,535; Figs 33,35; Col 17, lines 1-50) the plurality of capacitors being positioned on upper surfaces of the plurality of storage node structures, and being arranged in one-to-one correspondence with the plurality of storage node structures (as shown Figs 33,35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Burns, Jr.; Stuart Mcallister et al. (US 6013548; hereinafter Burns).
Regarding claim 14, Burns discloses the semiconductor structure according to claim 8, wherein the semiconductor structure further comprises: a filling dielectric layer (538; Fig 35, which is one of two example designs shown for capacitor 520 of Fig 33; Col 18, lines 19-26,60-66) the filling dielectric layer being positioned on an upper surface of the first isolation dielectric layer and an upper surface of the second isolation dielectric layer, and the filling dielectric layer being configured to fill up a spacing between adjacent two of the plurality of word line structures (although limitation of the last line is not shown in the figures, it would have been obvious to a person having ordinary skill in the art the spaces comprising Delta between wordlines 275 of Fig 27 would be filled with an insulating dielectric to prevent a short between adjacent word lines, such as by the filling dielectric layer 538 shown in Fig 35 from only one cross-sectional perspective, which is through the word lines rather than between them).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Burns, Jr.; Stuart Mcallister et al. (US 6013548; hereinafter Burns) in view of Lee; Min-Suk et al. (US 2009/0004861; hereinafter Lee).
Regarding claim 13, Burns discloses the semiconductor structure according to claim 12, wherein the protective layer further comprises spacers (270; Figs 31-33; Col 16, lines 58-61), the spacers being positioned on side walls of the second connection terminals (as shown in Figs 31-33), and the spacers being configured to wrap the second connection terminals (as shown in Figs 31-33).
Burns does not disclose the spacers being configured to wrap the patterned mask layer (245), and fill up a spacing between the first isolation dielectric layer and the patterned mask layer and a spacing between the second isolation dielectric layer and the patterned mask layer.
In the same field of endeavor, Lee discloses a similar semiconductor structure wherein a protective layer (401, 403; Fig 4H; ¶ [0033-35]) comprises spacers (403; Figs 4B-4H; ¶ [0035]), the spacers being positioned on side walls of second connection terminals (400A; Figs 4B-41), and the spacers being configured to wrap the second connection terminals and a patterned mask layer (401; Figs 4B-4H), and fill up a spacing between a first isolation dielectric layer (407, in the first, X-X' direction, extending between columns of pillars P, 408; Figs 4F-4G,41; ¶ [0044]) and the patterned mask layer and a spacing between a second isolation dielectric layer (407, in the second, Y-Y' direction) and the patterned mask layer.
Accordingly, it would have been obvious to a person having ordinary skill in the art that the spacers of claim 13 may be configured the manner of Lee. One may have been motivated to do this as an alternate method of manufacturing the semiconductor structure resulting in a functional equivalent. One would have had a reasonable expectation of success because of the similarity in the structures, materials and endeavors of Burns and Lee.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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