Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada (US 6,927,491) in view of KOBSAYASHI et al.(US 2011/0304059), further in view of SHIRASAKI et al.(US 20210143787) and further in view of Iwasaki et al. (US2005/0191473).
Regarding claim 14 Yamada discloses an electronic component with high coplanarity(fig 5), having a body(fig 5, 4) with a functional circuit(claim 1) and a mounting plane(fig 5, upper surface of item 4); a first electrode on said mounting plane with a first area(fig 5, 5) ;a second electrode on said mounting plane with a second area(fig 5, 6), wherein said first area is larger than said second area(claim 1, fig 3). Yamada does not disclose a groove on said mounting plane connecting said first electrode and said second electrode; wherein said first electrode and said second electrode comprise a conductive layer and at least one first plating layer over said conductive layer, and a thickness of said conductive layer of said first electrode is substantially equal to a thickness of said conductive layer of said second electrode, and a thickness of said first plating layer of said first electrode is substantially equal to a thickness of said first plating layer of said second electrode.
Regarding the groove, KOBSAYASHI et al. discloses a groove(fig 4B, 2b) on said mounting plane connecting said first electrode and said second electrode(fig 4B, 2a) showing this is done for stress dispersion Fig 4B). It would have been obvious to one skilled in the art at the time of the invention to use discloses a groove(fig 4B, 2b) on said mounting plane connecting said first electrode and said second electrode as shown by KOBSAYASHI et al., with the circuit board of Yamada, since this is commonly done for stress relief.
Regarding the first and second electrodes, although Yamada discloses the electrodes have the same height in the fig 5, Yamada does not specifically state they are the same height, SHIRASAKI et al. discloses wherein said first electrode and said second electrode(Fig 9A, 49) has a conductive layer (fig 9A, 49), and a thickness of said conductive layer of said first electrode is substantially equal to a thickness of said conductive layer of said second electrode(para 0103, states the electrodes have a height of 9 to 10um). It would have been obvious to one skilled in the art at the time of the invention to use a first electrode and said second electrode has a conductive layer, and a thickness of said conductive layer of said first electrode is substantially equal to a thickness of said conductive layer of said second electrode as shown by KOBSAYASHI et al., with the circuit board of Yamada, since this is commonly done for the simplification of the manufacturing process. .
Regarding the plating layers, Iwasaki et al. discloses at least one first plating layer(fig 2f, 6b) over said conductive layer made of copper(fig 2f, 3; para 0031), a thickness of said first plating layer of said first electrode is substantially equal to a thickness of said first plating layer of said second electrode (para 0012, stating the plating layer is uniform). It would have been obvious to one skilled in the art at the time of the invention to use a at least one first plating layer over said conductive layer, a thickness of said first plating layer of said first electrode is substantially equal to a thickness of said first plating layer of said second electrode as shown by Iwasaki et al., with the circuit board of Yamada, since this is commonly done for the to prevent the conductor made of copper from oxidizing.
Regarding claim 15, Yamada does not disclose a second plating layer between said first plating layer and said conductive layer, wherein a thickness of said second plating layer of said first electrode is substantially equal to a thickness of said second plating layer of said second electrode. Iwasaki et al. discloses a second plating layer(fig 2f, 6a) between said first plating layer(fig 2a, 6b) and said conductive layer(fig 2f, 3), wherein a thickness of said second plating layer of said first electrode is substantially equal to a thickness of said second plating layer of said second electrode. Iwasaki et al. disclose a second plating(fig 2f, 6a) layer between said first plating layer(fig 2a, 6b) and said conductive layer(fig 2f, 3), wherein a thickness of said second plating layer of said first electrode is substantially equal to a thickness of said second plating layer of said second electrode(para 0012, stating the plating layer is uniform). It would have been obvious to one skilled in the art at the time of the invention to use a at least one first plating layer over said conductive layer, a thickness of said first plating layer of said first electrode is substantially equal to a thickness of said first plating layer of said second electrode as shown by Iwasaki et al., with the circuit board of Yamada, since this is commonly done for the to prevent the conductor made of copper from oxidizing.
Regarding claim 16 Yamada discloses wherein said conductive layer(fig 5, 5, 6) is formed on said mounting plane with the same base level(fig 5, 4).
Regarding claim 17 Yamada does not disclose wherein a thickness difference between said first electrode and said second electrode is within 10 um. However, SHIRASAKI et al. discloses wherein said first electrode and said second electrode(Fig 9A, 49) has a conductive layer (fig 9A, 49), and a thickness of said conductive layer of said first electrode is substantially equal to a thickness of said conductive layer of said second electrode(para 0103, states the electrodes have a height of 9 to 10 um). It would have been obvious to one skilled in the art at the time of the invention to use a thickness difference between said first electrode and said second electrode is within 10 um as shown by SHIRASAKI et al., with the circuit board of Yamada, since this is commonly done for uniformity of the electrode helps when connecting a chip to them .
Regarding claim 18 Yamada discloses said first electrode is a grounding electrode electrically connected to a ground terminal of said functional circuit, and said second electrode is a signal electrode electrically connected to a signal terminal of said functional circuit(col 2, lines 65-67).
Regarding claim 19, a modified Yamada, as detailed in claim rejection 14 above, discloses wherein said first electrode and said second electrode have the same number of layer structures (the electrodes each have two plated layers).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada (US 6,927,491) in view of KOBSAYASHI et al.(US 2011/0304059), further in view of SHIRASAKI et al.(US 20210143787) and further in view of Iwasaki et al. (US2005/0191473) as detailed in claim rejection 14 above and further in view of HOTTA et al.(US 2013/0252443).
Regarding claim 20, a modified Yamada does not disclose wherein a spacing between said first electrode and said second electrode is within 200 pm.
However, HOTTA et al. discloses wherein a spacing between said first electrode and said second electrode is within 200 um(para 0185). It would have been obvious to one skilled in the art at the time of the invention to use wherein a spacing between said first electrode and said second electrode is within 200 um shown by KABE et al.., with the circuit board of Yamada, since Yamada does not disclose a spacing and this spacing is commonly done so as to provide for the needed miniaturization of today’s electronics.
Conclusion
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/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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