DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election Requirement filed 30 June 2025. Claims 1-20 are pending in this application and Claims 1-15 are withdrawn. Claims 16-20 are examined in this Office Action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the semiconductor device of Group II, on which Claims 16-20 read, in the reply filed on 30 June 2025 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “transistor layer stacked over the second wiring layer“ of Claims 19-20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 19, Claim 19 recites the limitation “the transistor layer including a second array of transistor pairs each having a cross-section having a similar structure as that of each of the first array of transistor pairs”. This is unclear due to the phrase “similar structure”. It is unclear what constitutes a “a cross-section having a similar structure as that of each of the first array of transistor pairs” (i.e. do the orientation of the transistors of the first and second arrays need to be the same, can there additional parts to the transistors that may differ, do materials need to be the same, etc…). For purposes of examination, “a cross-section having a similar structure as that of each of the first array of transistor pairs” is being interpreted as requiring all of the claimed structural limitations of the first array of transistor pairs, namely:
(from Claim 16) each transistor pair including a mandrel having two opposite sidewalls that are perpendicular to the substrate and extending along a direction of the first array of transistor pairs, each transistor pair including two transistors symmetrically disposed over the two opposite sidewalls of the respective mandrel.
(From Claim 17) wherein each of the two transistors has a channel over one of the two opposite sidewalls of the respective mandrel, a gate dielectric over the channel, and a gate electrode over the gate dielectric.
However, the phrase “similar structure” is not being interpreted as imposing any additional constraints (such as to orientation, materials, additional parts, etc…)
Regarding Claim 20, Claim 20 depends from Claim 19 and is rejected for the same reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Kawashima et. al (US 2006/0125025 A1).
Regarding Claim 16, Kawashima discloses (as shown in Fig. 6A, 8H, 9) A semiconductor device, comprising:
a substrate ([0092] glass substrate 1);
a first wiring layer ([0092] lower electrode (drain electrode) 4) over the substrate (1); (See Fig. 8H, showing the lower electrode 4 over the glass substrate 1)
and a first array of transistor pairs (Fig. 8H; See Fig. 8H, having channels 8 on the left and right side) extending over the first wiring layer (4), ([0106] Only two transistors are illustrated in FIG. 9. In a preferred embodiment, however, a lot of transistors are preferably integrated together on the same substrate.)
cross sections of each transistor pair (Fig. 8H) cutting through the first array (See Fig. 9, showing cross sections of 2 transistor pairs of the lots of transistors), the cross sections of each transistor pair (Fig. 8H) having a similar structure, (See Fig. 9, showing cross sections of 2 transistor pairs of the lots of transistors having similar structures)
each transistor pair (Fig. 8H) including a mandrel ([0092] an insulating film 9' to be the dielectric portion 9) having two opposite sidewalls (left, right) that are perpendicular to the substrate (1) (See Fig. 8H, showing the sidewalls of the dielectric portion 9 perpendicular to the substrate 1)
and extending along a direction of the first array of transistor pairs, (See Fig. 6A)
each transistor pair (Fig. 8H) including two transistors symmetrically disposed over the two opposite sidewalls of the respective mandrel (9). (See Fig. 8H, showing the channel regions 8 disposed on the left and right sidewalls of the dielectric portion 9)
Regarding Claim 17, Kawashima further discloses (as shown in Fig. 8H) wherein each of the two transistors has a channel ([0103] the channel region 8, made of the remaining nanowires 8') over one of the two opposite sidewalls of the respective mandrel (9), (See Fig. 8H, showing the channel regions 8 disposed on the left and right sidewalls of the dielectric portion 9)
a gate dielectric ([0100] gate insulating film 6) over the channel (8), (See Fig. 8H, showing the gate dielectric 6 disposed on the left and right channel regions 8)
and a gate electrode ([0100] gate electrode 5) over the gate dielectric (6). (See Fig. 8H, showing the gate electrode 5 disposed on the left and right gate dielectrics 6)
Regarding Claim 18, Kawashima further discloses (as shown in Fig. 8H) comprising a second wiring layer ([0092] upper electrode (source electrode) 7) in parallel with the first wiring layer (4) and above the first array of transistor pairs, (See Fig. 8H, showing the upper electrode 7 and the lower electrode 4 being parallel with the upper electrode 7 above the lower electrode 4) (See Fig. 8H, showing the upper electrode 7 above the channel regions 8)
the channel (8) of each of the two transistors being in electrical connection with the first wiring layer (4) providing a first source/drain (S/D) contact structure to the channel (8) ([0092] lower electrode (drain electrode) 4)
and with the second wiring layer (7) through a second S/D contact structure. ([0092] upper electrode (source electrode) 7)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima et. al (US 2006/0125025 A1) as applied to Claim 18 above, and further in view of Lee (US 2023/0107258 A1).
Regarding Claim 19, Kawashima fails to disclose a transistor layer stacked over the second wiring layer, the transistor layer including a second array of transistor pairs each having a cross-section having a similar structure as that of each of the first array of transistor pairs (Fig. 8H), channels of the second array of transistors being in electrical connection with S/D contact structures (7) provided in the second wiring layer.
Lee discloses (as shown in Fig. 2E) a transistor layer ([0025] upper-level vertical transistor) stacked over the second wiring layer ([0025] intermediate interconnect 202a), ([0025] The common-drain coupling is made by forming the upper-level vertical transistor on an intermediate interconnect 202a which is patterned over and coupled to the top diffusion region of the lower-level vertical transistor.)
the transistor layer (upper-level vertical transistor) including a second transistor ([0042] The upper-level vertical transistor comprises likewise a semiconductor pillar 204 standing on a first piece 202a of a conductive film, a gate dielectric 210, and a gate 212 with a gate extension 212a) each having a cross-section having a similar structure as that of each of the first transistors ([0042] The lower-level vertical transistor comprises a semiconductor pillar 104 standing on a piece 102 of a conductive film, a gate dielectric 110, and a gate 112 with a gate extension 112a), (See Fig. 2E, showing the cross-section of the upper and lower vertical transistors is similar.)
channels of the second transistor ([0042] semiconductor pillar 204) being in electrical connection with S/D contact structures provided in the second wiring layer ([0025] The common-drain coupling is made by forming the upper-level vertical transistor on an intermediate interconnect 202a which is patterned over and coupled to the top diffusion region of the lower-level vertical transistor).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Kawashima and Lee. Lee teaches that the upper-level and lower-level transistors can be coupled to form an inverter. ([0027] FIG. 2E illustrates a structure 200E, in which the vertical transistors of FIG. 2B are coupled as an inverter) It would have been obvious to have an upper-level transistor coupled to a lower-level transistor to create an inverter.
However, Lee fails to disclose the transistor layer (upper-level vertical transistor) including a second array of transistor pairs each having a cross-section having a similar structure as that of each of the first array of transistor pairs (lower-level vertical transistors),
It would have been obvious before the effective filing date of the application to have the transistor layer (upper-level vertical transistor) include a second array of transistor pairs (upper-level) each having a cross-section having a similar structure as that of each of the first array of transistor pairs (lower level). Kawashima teaches a first array of transistor pairs. ([0106] Only two transistors are illustrated in FIG. 9. In a preferred embodiment, however, a lot of transistors are preferably integrated together on the same substrate.) It would have been obvious for the upper-level transistors to form an array in order to create an array of inverters.
Lee teaches that the cross-sections of the upper transistors are similar to the cross-section of the lower transistors (See Fig. 2E). Since the lower transistors in Kawashima are transistor pairs, it would have been obvious for the upper transistors to comprise transistor pairs with a similar cross-section as the lower transistor pairs.
Regarding Claim 20, Kawashima further discloses (as shown in Fig. 8H) wherein the first wiring layer (4) and the second wiring layer (7) each include one or more metal layers, ([0088] The lower and upper electrodes 4 and 7 may be made of any of various electrically conductive materials. Since the Ge nanowires are grown on the lower electrode 4, the lower electrode 4 is preferably made of a metal such as gold, silver or platinum, a cobalt silicide or a nickel silicide, for example.)
It would have been obvious before the effective filing date of the application to have the first array of transistor pairs (lower-level) and the second array of transistor pairs (upper-level) extend in a same direction or different directions. Lee discloses (as shown in Fig. 2E) that the upper-level and lower-level transistors are disposed in the same orientation. (See Fig. 2E) Therefore, it would have been obvious for the first transistor pairs and second transistor pairs to extend in the same direction, since it would be obvious to orient them in the same direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Forbes (US 2010/0289559 A1): Forbes discloses (as shown in Fig. 6A, 9) a pair of transistors ([0024] tunneling NMOS transistors 350, 351) located on opposite side of a mandrel ([0024] oxide pillar 330) with separate source/drains ([0030] their respective source 310, 301 and drain 302, 311 regions.)
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/J.J.G./Examiner, Art Unit 2893
/Britt D Hanley/Supervisory Patent Examiner, Art Unit 2893